R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 406

• Manufacturer Part Number: R5F21324ANSP#U1
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Ar

Specifications of R5F21324ANSP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 376 of 583
Figure 24.5
24.4.2
Figure 24.5 shows an Example of Synchronous Serial Communication Unit Operation for Data Transmission
(Clock Synchronous Communication Mode, 8-Bit SSU Data Transfer Length). During data transmission, the
synchronous serial communication unit operates as described below (The data transfer length can be set from 8
to 16 bits using the SSBR register).
When synchronous serial communication unit is set as a master device, it outputs a synchronous clock and data.
When synchronous serial communication unit is set as a slave device, it outputs data synchronized with the
input clock.
When the TE bit is set to 1 (transmit enabled) before writing the transmit data to the SSTDR register, the TDRE
bit is automatically set to 0 (data not transferred from registers SSTDR to SSTRSR) and the data is transferred
from registers SSTDR to SSTRSR.
After the TDRE bit is set to 1 (data transferred from registers SSTDR to SSTRSR), transmission starts. When
the TIE bit in the SSER register is set to 1, the TXI interrupt request is generated. When one frame of data is
transferred while the TDRE bit is set to 0, data is transferred from registers SSTDR to SSTRSR and
transmission of the next frame is started. If the 8th bit is transmitted while the TDRE bit is set to 1, the TEND
bit in the SSSR register is set to 1 (the TDRE bit is set to 1 when the last bit of the transmit data is transmitted)
and the state is retained. The TEI interrupt request is generated when the TEIE bit in the SSER register is set to
1 (transmit-end interrupt request enabled). The SSCK pin is fixed “H” after transmit-end.
Transmission cannot be performed while the ORER bit in the SSSR register is set to 1 (overrun error). Confirm
that the ORER bit is set to 0 before transmission.
Figure 24.6 shows a Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode).
TDRE bit in
SSSR register
TEND bit in
SSSR register
Data Transmission
Processing
by program
• SSUMS = 0 (clock synchronous communication mode), CPHS = 0 (data change at
(Clock Synchronous Communication Mode, 8-Bit SSU Data Transfer Length)
Preliminary specification
Specifications in this manual are tentative and subject to change.
Example of Synchronous Serial Communication Unit Operation for Data Transmission
odd numbers), CPOS = 0 (“H” when clock stops), and BS3 to BS0 = 1000b (8 bits)
SSCK
SSO
1
0
1
0
Write data to SSTDR register
Nov 05, 2008
TXI interrupt request generation
b0
b1
1 frame
24. Synchronous Serial Communication Unit (SSU)
b7
b0
TEI interrupt request
generation
BS0 to BS3: Bits in SSBR register
CPHS, CPOS: Bits in SSMR register
SSUMS: Bit in SSMR2 register
b1
1 frame
b7