R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 359

MCU 1KB FLASH 16K ROM 20-LSSOP

R5F21324ANSP#U1

Manufacturer Part Number
R5F21324ANSP#U1
Description
MCU 1KB FLASH 16K ROM 20-LSSOP
Manufacturer
Renesas Electronics America
Series
R8C/3x/32Ar
Datasheet

Specifications of R5F21324ANSP#U1

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
15
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-LSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F21324ANSP#U1
Manufacturer:
Renesas Electronics America
Quantity:
135
Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 329 of 583
Figure 22.4
22.3.1
22.3.2
If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode, follow
the procedures below:
• Resetting the U2RB register
(1) Set the RE bit in the U2C1 register to 0 (reception disabled).
(2) Set bits SMD2 to SMD0 in the U2MR register to 000b (serial interface disabled).
(3) Set bits SMD2 to SMD0 in the U2MR register to 001b (clock synchronous serial I/O mode).
(4) Set the RE bit in the U2C1 register to 1 (reception enabled).
• Resetting the U2TB register
(1) Set bits SMD2 to SMD0 in the U2MR register to 000b (serial interface disabled).
(2) Set bits SMD2 to SMD0 in the U2MR register to 001b (clock synchronous serial I/O mode).
(3) Write 1 to the TE bit in the U2C1 register (transmission enabled), regardless of the TE bit value in the
Use the CKPOL bit in the U2C0 register to select the transfer clock polarity. Figure 22.4 shows the Transfer
Clock Polarity.
(1) CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge and
(2) CKPOL bit in U2C0 register = 1 (transmit data output at the rising edge and
U2C2 register.
CLK2
TXD2
RXD2
CLK2
TXD2
RXD2
The above applies when:
Measure for Dealing with Communication Errors
CLK Polarity Select Function
receive data input at the rising edge of the transfer clock)
receive data input at the falling edge of the transfer clock)
UFORM bit in U2C0 register = 0 (LSB first)
U2LCH bit in U2C1 register = 0 (not inverted)
Preliminary specification
Specifications in this manual are tentative and subject to change.
Transfer Clock Polarity
D0
D0
D0
D0
Nov 05, 2008
D1
D1
D1
D1
D2
D2
D2
D2
D3
D3
D3
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
“H” output from CLK2 pin
“L” output from CLK2 pin
during no transfer
during no transfer
22. Serial Interface (UART2)

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