MC68HC16Z1CEH16 Freescale Semiconductor, MC68HC16Z1CEH16 Datasheet - Page 103

• Manufacturer Part Number: MC68HC16Z1CEH16
• Description: IC MCU 16BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Processor Series: HC16Z
• Core: CPU16
• Data Bus Width: 16 bit
• Controller Family/series: 68HC16
• No. Of I/o's: 26
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.14.4.4 BDM Commands
4.14.4.5 Returning from BDM
M68HC16 Z SERIES
USER’S MANUAL
of BKPT or execution of the BGND instruction. IPIPE0 and IPIPE1 change function be-
fore an exception signal can be generated. The development system must use
FREEZE assertion as an indication that BDM has been entered. When BDM is exited,
FREEZE is negated before initiation of normal bus cycles. IPIPE0 and IPIPE1 are valid
when normal instruction prefetch begins.
Commands consist of one 16-bit operation word and can include one or more 16-bit
extension words. Each incoming word is read as it is assembled by the serial interface.
The microcode routine corresponding to a command is executed as soon as the com-
mand is complete. Result operands are loaded into the output shift register to be shift-
ed out as the next command is read. This process is repeated for each command until
the CPU returns to normal operating mode. The BDM command set is summarized in
Table
mand glossary.
BDM is terminated when a resume execution (GO) command is received. GO refills
the instruction pipeline from address (PK : PC – $0006). FREEZE is negated before
the first prefetch. Upon negation of FREEZE, the BDM serial subsystem is disabled
and the DSO/DSI signals revert to IPIPE0/IPIPE1 functionality.
Read Program Memory
Write Program Memory
Execute from Current
Read MAC Registers
Write MAC Registers
Read Data Memory
Write Data Memory
Read PC and SP
4-7. Refer to the CPU16 Reference Manual (CPU16RM/AD) for a BDM com-
Write PC and SP
Read Registers
Write Registers
Null Operation
Command
from Mask
from Mask
PK : PC
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 4-7 Command Summary
Mnemonic
WREGM
WDMEM
WPMEM
CENTRAL PROCESSING UNIT
WRMAC
RDMEM
RREGM
RDMAC
WPCSP
RPMEM
RPCSP
NOP
GO
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Read contents of registers specified by command
word register mask
Write to registers specified by command word
register mask
Read contents of entire multiply and accumulate
register set
Write to entire multiply and accumulate register set
Read contents of program counter and stack pointer
Write to program counter and stack pointer
Read byte from specified 20-bit address in data
space
Write byte to specified 20-bit address in data space
Read word from specified 20-bit address in program
space
Write word to specified 20-bit address in program
space
Instruction pipeline flushed and refilled; instructions
executed from current PC – $0006
Null command performs no operation
Description
4-43