MC68HC16Z1CEH16 Freescale Semiconductor, MC68HC16Z1CEH16 Datasheet - Page 444

• Manufacturer Part Number: MC68HC16Z1CEH16
• Description: IC MCU 16BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Processor Series: HC16Z
• Core: CPU16
• Data Bus Width: 16 bit
• Controller Family/series: 68HC16
• No. Of I/o's: 26
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PACTL/PACNT — Pulse Accumulator Control Register/Counter
OC1M[5:1] — OC1 Mask Field
OC1D[5:1] — OC1 Data Field
D.8.6 Timer Counter Register
TCNT — Timer Counter Register
D.8.7 Pulse Accumulator Control Register/Counter
PAIS — PAI Pin State (Read Only)
PAEN — Pulse Accumulator Enable
PAMOD — Pulse Accumulator Mode
PEDGE — Pulse Accumulator Edge Control
D-70
PAIS
15
U
RESET:
OC1M[5:1] correspond to OC[5:1].
OC1D[5:1] correspond to OC[5:1].
TCNT is the 16-bit free-running counter associated with the input capture, output com-
pare, and pulse accumulator functions of the GPT module.
PACTL enables the pulse accumulator and selects either event counting or gated
mode. In event counting mode, PACNT is incremented each time an event occurs. In
gated mode, it is incremented by an internal clock.
The effects of PAMOD and PEDGE are shown in
PAEN
0 = Corresponding output compare pin is not affected by OC1 compare.
1 = Corresponding output compare pin is affected by OC1 compare.
0 = If OC1 mask bit is set, clear the corresponding output compare pin on OC1
1 = If OC1 mask bit is set, the set corresponding output compare pin on OC1
0 = Pulse accumulator disabled.
1 = Pulse accumulator enabled.
0 = External event counting.
1 = Gated time accumulation.
14
0
match.
match.
PAMOD PEDGE PCLKS
13
0
12
0
Freescale Semiconductor, Inc.
11
0
For More Information On This Product,
I4/O5
10
0
Go to: www.freescale.com
REGISTER SUMMARY
PACLK[1:0]
9
0
8
0
7
0
6
0
Table
PULSE ACCUMULATOR COUNTER
5
0
D-44.
4
0
3
0
M68HC16 Z SERIES
USER’S MANUAL
2
0
$YFF90C
$YFF90A
1
0
0
0