MC68HC16Z1CEH16 Freescale Semiconductor, MC68HC16Z1CEH16 Datasheet - Page 262

• Manufacturer Part Number: MC68HC16Z1CEH16
• Description: IC MCU 16BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Processor Series: HC16Z
• Core: CPU16
• Data Bus Width: 16 bit
• Controller Family/series: 68HC16
• No. Of I/o's: 26
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.4.5.8 Receiver Wake-Up
10.4.5.9 Internal Loop
10-22
In some applications, software overhead can cause a bit-time of logic level one to oc-
cur between frames. This bit-time does not affect content, but if it occurs after a frame
of ones when short detection is enabled, the receiver flags an idle line.
When the ILIE bit in SCCR1 is set, an interrupt request is generated when the IDLE
flag is set. The flag is cleared by reading SCSR and SCDR in sequence. IDLE is not
set again until after at least one frame has been received (RDRF = 1). This prevents
an extended idle interval from causing more than one interrupt.
The receiver wake-up function allows a transmitting device to direct a transmission to
a single receiver or to a group of receivers by sending an address frame at the start of
a message. Hardware activates each receiver in a system under certain conditions.
Resident software must process address information and enable or disable receiver
operation.
A receiver is placed in wake-up mode by setting the RWU bit in SCCR1. While RWU
is set, receiver status flags and interrupts are disabled. Although the CPU32 can clear
RWU, it is normally cleared by hardware during wake-up.
The WAKE bit in SCCR1 determines which type of wake-up is used. When WAKE =
0, idle-line wake-up is selected. When WAKE = 1, address-mark wake-up is selected.
Both types require a software-based device addressing and recognition scheme.
Idle-line wake-up allows a receiver to sleep until an idle line is detected. When an idle-
line is detected, the receiver clears RWU and wakes up. The receiver waits for the first
frame of the next transmission. The byte is received normally, transferred to the RDR,
and the RDRF flag is set. If software does not recognize the address, it can set RWU
and put the receiver back to sleep. For idle-line wake-up to work, there must be a min-
imum of one frame of idle line between transmissions. There must be no idle time be-
tween frames within a transmission.
Address-mark wake-up uses a special frame format to wake up the receiver. When the
MSB of an address-mark frame is set, that frame contains address information. The
first frame of each transmission must be an address frame. When the MSB of a frame
is set, the receiver clears RWU and wakes up. The byte is received normally, trans-
ferred to the RDR, and the RDRF flag is set. If software does not recognize the ad-
dress, it can set RWU and put the receiver back to sleep. Address-mark wake-up
allows idle time between frames and eliminates idle time between transmissions. How-
ever, there is a loss of efficiency because of an additional bit-time per frame.
The LOOPS bit in SCCR1 controls a feedback path in the data serial shifter. When
LOOPS is set, the SCI transmitter output is fed back into the receive serial shifter. TXD
is asserted (idle line). Both transmitter and receiver must be enabled before entering
loop mode.
MULTICHANNEL COMMUNICATION INTERFACE
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