MC68HC16Z1CEH16 Freescale Semiconductor, MC68HC16Z1CEH16 Datasheet - Page 424

• Manufacturer Part Number: MC68HC16Z1CEH16
• Description: IC MCU 16BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Processor Series: HC16Z
• Core: CPU16
• Data Bus Width: 16 bit
• Controller Family/series: 68HC16
• No. Of I/o's: 26
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

SPCR3 — QSPI Control Register
SPSR — QSPI Status Register
SPIFIE — SPI Finished Interrupt Enable
WREN — Wrap Enable
WRTO — Wrap To
Bit 12 — Not Implemented
ENDQP[3:0] — Ending Queue Pointer
Bits [7:4] — Not Implemented
NEWQP[3:0] — New Queue Pointer Value
D.6.13 QSPI Control Register 3
Bits [15:11] — Not Implemented
LOOPQ — QSPI Loop Mode
D-50
15
RESET:
SPCR2 contains QSPI queue pointers, wraparound mode control bits, and an interrupt
enable bit. SPCR2 is buffered. New SPCR2 values become effective only after com-
pletion of the current serial transfer. Rewriting NEWQP in SPCR2 causes execution to
restart at the designated location. Reads of SPCR2 return the value of the register, not
the buffer.
This field contains the last QSPI queue address.
This field contains the first QSPI queue address.
SPCR3 contains the loop mode enable bit, halt and mode fault interrupt enable, and
the halt control bit. SPCR3 must be initialized before QSPI operation begins. Writing
a new value to SPCR3 while the QSPI is enabled disrupts operation. SPSR contains
information concerning the current serial transmission.
LOOPQ controls feedback on the data serializer for testing.
0 = QSPI interrupts disabled.
1 = QSPI interrupts enabled.
0 = Wraparound mode disabled.
1 = Wraparound mode enabled.
0 = Wrap to pointer address $0.
1 = Wrap to address in NEWQP.
0 = Feedback path disabled.
1 = Feedback path enabled.
14
NOT USED
13
12
Freescale Semiconductor, Inc.
11
For More Information On This Product,
LOOPQ
10
0
Go to: www.freescale.com
REGISTER SUMMARY
HMIE
9
0
HALT
8
0
SPIF
7
0
MODF
6
0
HALTA
5
0
USED
NOT
4
3
0
M68HC16 Z SERIES
USER’S MANUAL
CPTQP[3:0]
2
0
$YFFC1E
$YFFC1F
1
0
0
0