MC68HC16Z1CEH16 Freescale Semiconductor, MC68HC16Z1CEH16 Datasheet - Page 234

• Manufacturer Part Number: MC68HC16Z1CEH16
• Description: IC MCU 16BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Processor Series: HC16Z
• Core: CPU16
• Data Bus Width: 16 bit
• Controller Family/series: 68HC16
• No. Of I/o's: 26
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.4.1 SCI Registers
9.4.1.1 Control Registers
9.4.1.2 Status Register
9.4.1.3 Data Register
9-24
The SCI programming model includes the QSM global and pin control registers, and
four SCI registers. There are two SCI control registers (SCCR0 and SCCR1), one sta-
tus register (SCSR), and one data register (SCDR). Refer to
ule
SCCR0 contains the baud rate selection field. Baud rate must be set before the SCI is
enabled. This register can be read or written.
SCCR1 contains a number of SCI configuration parameters, including transmitter and
receiver enable bits, interrupt enable bits, and operating mode enable bits. This regis-
ter can be read or written at any time. The SCI can modify the RWU bit under certain
circumstances.
Changing the value of SCI control bits during a transfer may disrupt operation. Before
changing register values, allow the SCI to complete the current transfer, then disable
the receiver and transmitter.
SCSR contains flags that show SCI operating conditions. These flags are cleared ei-
ther by SCI hardware or by reading SCSR, then reading or writing SCDR. A long-word
read can consecutively access both SCSR and SCDR. This action clears receiver sta-
tus flag bits that were set at the time of the read, but does not clear TDRE or TC flags.
If an internal SCI signal for setting a status bit comes after reading the asserted status
bits, but before reading or writing SCDR, the newly set status bit is not cleared. SCSR
must be read again with the bit set, and SCDR must be read or written before the sta-
tus bit is cleared.
Reading either byte of SCSR causes all 16 bits to be accessed, and any status bit al-
ready set in either byte is cleared on a subsequent read or write of SCDR.
SCDR contains two data registers at the same address. The receive data register
(RDR) is a read-only register that contains data received by the SCI. Data enters the
receive serial shifter and is transferred to RDR. The transmit data register (TDR) is a
write-only register that contains data to be transmitted. Data is first written to TDR,
then transferred to the transmit serial shifter, where additional format bits are added
before transmission. R[7:0]/T[7:0] contain either the first eight data bits received when
SCDR is read, or the first eight data bits to be transmitted when SCDR is written. R8/
T8 are used when the SCI is configured for 9-bit operation. When the SCI is configured
for 8-bit operation, they have no meaning or effect.
for register bit and field definitions.
Freescale Semiconductor, Inc.
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