MC68HC16Z1CEH16 Freescale Semiconductor, MC68HC16Z1CEH16 Datasheet - Page 70

• Manufacturer Part Number: MC68HC16Z1CEH16
• Description: IC MCU 16BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Processor Series: HC16Z
• Core: CPU16
• Data Bus Width: 16 bit
• Controller Family/series: 68HC16
• No. Of I/o's: 26
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.6.2 Extended Addressing Modes
4.6.3 Indexed Addressing Modes
4.6.4 Inherent Addressing Mode
4.6.5 Accumulator Offset Addressing Mode
4.6.6 Relative Addressing Modes
4.6.7 Post-Modified Index Addressing Mode
4-10
Regular extended mode instructions contain ADDR[15:0] in the word following the op-
code. The effective address is formed by concatenating the EK field and the 16-bit byte
address. EXT20 mode is used only by the JMP and JSR instructions. These instruc-
tions contain a 20-bit effective address that is zero-extended to 24 bits to give the in-
struction an even number of bytes.
In the indexed modes, registers IX, IY, and IZ, together with their associated extension
fields, are used to calculate the effective address.
For 8-bit indexed modes an 8-bit unsigned offset contained in the instruction is added
to the value contained in an index register and its extension field.
For 16-bit modes, a 16-bit signed offset contained in the instruction is added to the val-
ue contained in an index register and its extension field.
For 20-bit modes, a 20-bit signed offset (zero-extended to 24 bits) is added to the val-
ue contained in an index register. These modes are used for JMP and JSR instructions
only.
Inherent mode instructions use information directly available to the processor to deter-
mine the effective address. Operands, if any, are system resources and are thus not
fetched from memory.
Accumulator offset modes form an effective address by sign-extending the content of
accumulator E to 20 bits, then adding the result to an index register and its associated
extension field. This mode allows use of an index register and an accumulator within
a loop without corrupting accumulator D.
Relative modes are used for branch and long branch instructions. If a branch condition
is satisfied, a byte or word signed two’s complement offset is added to the concatenat-
ed PK field and program counter. The new PK : PC value is the effective address.
Post-modified index mode is used by the MOVB and MOVW instructions. A signed 8-
bit offset is added to index register X after the effective address formed by XK : IX is
used.
Freescale Semiconductor, Inc.
For More Information On This Product,
CENTRAL PROCESSOR UNIT
Go to: www.freescale.com
M68HC16 Z SERIES
USER’S MANUAL