MC68HC16Z1CEH16 Freescale Semiconductor, MC68HC16Z1CEH16 Datasheet - Page 442

IC MCU 16BIT 16MHZ 132-PQFP

MC68HC16Z1CEH16

Manufacturer Part Number
MC68HC16Z1CEH16
Description
IC MCU 16BIT 16MHZ 132-PQFP
Manufacturer
Freescale Semiconductor
Series
HC16r
Datasheets

Specifications of MC68HC16Z1CEH16

Core Processor
CPU16
Core Size
16-Bit
Speed
16MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
132-QFP
Processor Series
HC16Z
Core
CPU16
Data Bus Width
16 bit
Controller Family/series
68HC16
No. Of I/o's
26
Ram Memory Size
1KB
Cpu Speed
16MHz
No. Of Timers
2
Embedded Interface Type
QSPI, SCI
Rohs Compliant
Yes
Package
132PQFP
Family Name
HC16
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Number Of Programmable I/os
16
On-chip Adc
8-chx10-bit
Number Of Timers
11
Data Ram Size
1 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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STOP — Stop Clocks
FRZ1 — Not Implemented
FRZ0 — FREEZE Assertion Response
STOPP — Stop Prescaler
INCP — Increment Prescaler
SUPV — Supervisor/Unrestricted Data Space
IARB[3:0] — Interrupt Arbitration ID
D.8.2 GPT Test Register
GPTMTR — GPT Module Test Register
D.8.3 GPT Interrupt Configuration Register
ICR — GPT Interrupt Configuration Register
IPA[3:0] — Interrupt Priority Adjust
D-68
15
0
RESET:
This bit has no effect because the CPU16 always operates in supervisor mode.
The IARB field is used to arbitrate between simultaneous interrupt requests of the
same priority. Each module that can generate interrupt requests must be assigned a
unique, non-zero IARB field value.
Used for factory test only.
ICR fields determine internal and external interrupt priority, and provide the upper nib-
ble of the interrupt vector number supplied to the CPU when an interrupt is acknowl-
edged.
This field specifies which GPT interrupt source is given highest internal priority. Refer
to
Table
0 = GPT clock operates normally.
1 = GPT clock is stopped.
0 = Ignore IMB FREEZE signal.
1 = FREEZE the current state of the GPT.
0 = Normal operation.
1 = Stop prescaler and pulse accumulator from incrementing. Ignore changes to
0 = Has no effect.
1 = If STOPP is asserted, increment prescaler once and clock input synchronizers
14
0
IPA[3:0]
input pins.
once.
D-43.
13
0
12
0
Freescale Semiconductor, Inc.
11
0
0
For More Information On This Product,
10
0
Go to: www.freescale.com
IPL[2:0]
REGISTER SUMMARY
9
0
8
0
7
0
6
0
IVBA[3:0]
5
0
4
0
3
0
0
M68HC16 Z SERIES
USER’S MANUAL
2
0
0
$YFF902
$YFF904
1
0
0
0
0
0

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