MC68HC16Z1CEH16 Freescale Semiconductor, MC68HC16Z1CEH16 Datasheet - Page 113

IC MCU 16BIT 16MHZ 132-PQFP

MC68HC16Z1CEH16

Manufacturer Part Number
MC68HC16Z1CEH16
Description
IC MCU 16BIT 16MHZ 132-PQFP
Manufacturer
Freescale Semiconductor
Series
HC16r
Datasheets

Specifications of MC68HC16Z1CEH16

Core Processor
CPU16
Core Size
16-Bit
Speed
16MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
132-QFP
Processor Series
HC16Z
Core
CPU16
Data Bus Width
16 bit
Controller Family/series
68HC16
No. Of I/o's
26
Ram Memory Size
1KB
Cpu Speed
16MHz
No. Of Timers
2
Embedded Interface Type
QSPI, SCI
Rohs Compliant
Yes
Package
132PQFP
Family Name
HC16
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Number Of Programmable I/os
16
On-chip Adc
8-chx10-bit
Number Of Timers
11
Data Ram Size
1 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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M68HC16 Z SERIES
USER’S MANUAL
1. MAINTAIN LOW LEAKAGE ON THE XFC NODE. REFER TO APPENDIX A ELECTRICAL CHARACTERISTICS FOR MORE INFORMATION.
2. RECOMMENDED LOOP FILTER FOR REDUCED SENSITIVITY TO LOW FREQUENCY NOISE.
The synthesizer locks when the VCO frequency is equal to f
by the filter time constant and by the amount of difference between the two comparator
inputs. Whenever a comparator input changes, the synthesizer must relock. Lock sta-
tus is shown by the SLOCK bit in SYNCR. During power-up, the MCU does not come
out of reset until the synthesizer locks. Crystal type, characteristic frequency, and lay-
out of external oscillator circuitry affect lock time.
When the clock synthesizer is used, SYNCR determines the system clock frequency
and certain operating parameters. The W and Y[5:0] bits are located in the PLL feed-
back path, enabling frequency multiplication by a factor of up to 256. When the W or
Y values change, VCO frequency changes, and there is a VCO relock delay. The SYN-
CR X bit controls a divide-by circuit that is not in the synthesizer feedback loop. When
X = 0 (reset state), a divide-by-four circuit is enabled, and the system clock frequency
is one-fourth the VCO frequency (f
and system clock frequency is one-half the VCO frequency (f
delay when clock speed is changed by the X bit.
When a slow reference is used, one W bit and six Y bits are located in the PLL feed-
back path, enabling frequency multiplication by a factor of up to 256. The X bit is lo-
cated in the VCO clock output path to enable dividing the system clock frequency by
two without disturbing the PLL.
When using a slow reference, the clock frequency is determined by SYNCR bit set-
tings as follows:
The reset state of SYNCR ($3F00) results in a power-on f
is 32.768 kHz.
V
SS
NORMAL OPERATING ENVIRONMENT
C3
C4
0.01 F
0.1 F
Figure 5-5 System Clock Filter Networks
Freescale Semiconductor, Inc.
For More Information On This Product,
C1
0.1 F
SYSTEM INTEGRATION MODULE
Go to: www.freescale.com
f
XFC
V
sys
DDSYN
1
VCO
=
4f
). When X = 1, a divide-by-two circuit is enabled
ref
Y
+
1
V
SS
2
HIGH-STABILITY OPERATING ENVIRONMENT
C3
C4
0.01 F
0.1 F
2W
+
X
sys
ref
VCO
of 8.388 MHz when f
. Lock time is affected
). There is no relock
C1
0.1 F
C2
0.01 F
NORMAL/HIGH-STABILITY XFC CONN
R1
18 k
XFC
V
DDSYN
1, 2
5-7
ref

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