MC68HC16Z1CEH16 Freescale Semiconductor, MC68HC16Z1CEH16 Datasheet - Page 423

IC MCU 16BIT 16MHZ 132-PQFP

MC68HC16Z1CEH16

Manufacturer Part Number
MC68HC16Z1CEH16
Description
IC MCU 16BIT 16MHZ 132-PQFP
Manufacturer
Freescale Semiconductor
Series
HC16r
Datasheets

Specifications of MC68HC16Z1CEH16

Core Processor
CPU16
Core Size
16-Bit
Speed
16MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
132-QFP
Processor Series
HC16Z
Core
CPU16
Data Bus Width
16 bit
Controller Family/series
68HC16
No. Of I/o's
26
Ram Memory Size
1KB
Cpu Speed
16MHz
No. Of Timers
2
Embedded Interface Type
QSPI, SCI
Rohs Compliant
Yes
Package
132PQFP
Family Name
HC16
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Number Of Programmable I/os
16
On-chip Adc
8-chx10-bit
Number Of Timers
11
Data Ram Size
1 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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DSCKL[6:0] — Delay before SCK
DTL[7:0] — Length of Delay after Transfer
D.6.12 QSPI Control Register 2
SPCR2 — QSPI Control Register 2
M68HC16 Z SERIES
USER’S MANUAL
RESET:
SPIFIE
15
0
When the DSCK bit is set in a command RAM byte, this field determines the length of
the delay from PCS valid to SCK transition. PCS can be any of the four peripheral chip-
select pins. The following equation determines the actual delay before SCK:
where DSCKL[6:0] is in the range of one to 127.
When DSCK is zero in a command RAM byte, then DSCKL[6:0] is not used. Instead,
the PCS valid to SCK transition is one-half the SCK period.
When the DT bit is set in a command RAM byte, this field determines the length of the
delay after a serial transfer. The following equation is used to calculate the delay:
where DTL is in the range of one to 255.
A zero value for DTL[7:0] causes a delay-after-transfer value of 8192
If DT is zero in a command RAM byte, a standard delay is inserted:
Delay after transfer can be used to provide a peripheral deselect interval. A delay can
also be inserted between consecutive transfers to allow serial A/D converters to com-
plete conversion. This is controlled by the DT bit in a command RAM byte.
WREN
14
0
WRTO
13
0
12
0
0
Freescale Semiconductor, Inc.
11
For More Information On This Product,
0
Delay after Transfer
Standard Delay after Transfer
PCS to SCK Delay
10
ENDQP[3:0]
0
Go to: www.freescale.com
REGISTER SUMMARY
9
0
8
0
7
0
0
=
=
32 DTL[7:0]
----------------------------------- -
DSCKL[6:0]
------------------------------ -
6
0
0
f
f
sys
5
0
0
sys
=
------- -
f
17
sys
4
0
0
3
0
NEWQP[3:0]
2
0
f
sys
$YFFC1C
.
1
0
D-49
0
0

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