MC68HC16Z1CEH16 Freescale Semiconductor, MC68HC16Z1CEH16 Datasheet - Page 446

• Manufacturer Part Number: MC68HC16Z1CEH16
• Description: IC MCU 16BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Processor Series: HC16Z
• Core: CPU16
• Data Bus Width: 16 bit
• Controller Family/series: 68HC16
• No. Of I/o's: 26
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TMSK1/TMSK2 — Timer Interrupt Mask Registers 1–2
D.8.10 Input Capture 4/Output Compare 5 Register
TI4/O5 — Input Capture 4/Output Compare 5 Register
D.8.11 Timer Control Registers 1 and 2
TCTL1/TCTL2 — Timer Control Registers 1–2
OM/OL[5:2] — Output Compare Mode Bits and Output Compare Level Bits
EDGE[4:1] — Input Capture Edge Control
D.8.12 Timer Interrupt Mask Registers 1 and 2
D-72
I4/O5I
OM5
15
15
0
0
RESET:
RESET:
This register serves either as input capture register 4 or output compare register 5, de-
pending on the state of I4/O5 in PACTL. It is reset to $FFFF.
TCTL1 determines output compare mode and output logic level. TCTL2 determines
the type of input capture to be performed.
Each pair of bits specifies an action to be taken when output comparison is successful.
Refer to
Each pair of bits configures input sensing logic for the corresponding input capture.
Refer to
OL5
14
14
0
0
Table
Table
OM4
13
13
0
0
OCI[4:1]
OL4
12
12
D-46.
D-47.
0
0
OM/OL[5:2]
EDGE[4:1]
00
01
10
11
00
01
10
11
Freescale Semiconductor, Inc.
OM3
11
11
0
0
For More Information On This Product,
Table D-46 OM/OL[5:2] Effects
Table D-47 EDGE[4:1] Effects
OL3
10
10
0
0
Go to: www.freescale.com
ICI[3:1]
REGISTER SUMMARY
OM2
9
0
9
0
Capture on any (rising or falling) edge
Timer disconnected from output logic
Clear OCx output line to zero
OL2
Capture on falling edge only
Capture on rising edge only
8
0
Set OCx output line to one
8
0
Toggle OCx output line
Capture disabled
EDG4B EDG4A EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A
Configuration
Action Taken
TOI
7
0
7
0
6
0
0
6
0
PAOVI
5
0
5
0
PAII
4
0
4
0
CPROUT
3
0
3
0
M68HC16 Z SERIES
USER’S MANUAL
2
0
2
0
$YFF91C
$YFF91E
$YFF920
CPR[2:0]
1
0
1
0
0
0
0
0