MC68HC16Z1CEH16 Freescale Semiconductor, MC68HC16Z1CEH16 Datasheet - Page 260

• Manufacturer Part Number: MC68HC16Z1CEH16
• Description: IC MCU 16BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Processor Series: HC16Z
• Core: CPU16
• Data Bus Width: 16 bit
• Controller Family/series: 68HC16
• No. Of I/o's: 26
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.4.5.6 Receiver Operation
10-20
The state of the serial shifter is checked when the TE bit is set. If TC = 1, an idle frame
is transmitted as a preamble to the following data frame. If TC = 0, the current opera-
tion continues until the final bit in the frame is sent, then the preamble is transmitted.
The TC bit is set at the end of preamble transmission.
The SBK bit in SCCR1 is used to insert break frames in a transmission. A non-zero
integer number of break frames is transmitted while SBK is set. Break transmission
begins when SBK is set, and ends with the transmission in progress at the time either
SBK or TE is cleared. If SBK is set while a transmission is in progress, that transmis-
sion finishes normally before the break begins. To assure the minimum break time,
toggle SBK quickly to one and back to zero. The TC bit is set at the end of break trans-
mission. After break transmission, at least one bit-time of logic level one (mark idle) is
transmitted to ensure that a subsequent start bit can be detected.
If TE remains set, after all pending idle, data and break frames are shifted out, TDRE
and TC are set and TXD is held at logic level one (mark).
When TE is cleared, the transmitter is disabled after all pending idle, data, and break
frames are transmitted. The TC flag is set, and control of the TXD pin reverts to MPAR
and MDDR. Buffered data is not transmitted after TE is cleared. To avoid losing data
in the buffer, do not clear TE until TDRE is set.
Some serial communication systems require a mark on the TXD pin even when the
transmitter is disabled. Configure the TXD pin as an output, then write a one to PQS7.
When the transmitter releases control of the TXD pin, it reverts to driving a logic one
output.
To insert a delimiter between two messages, to place non-listening receivers in wake-
up mode between transmissions, or to signal a retransmission by forcing an idle line,
clear and then set TE before data in the serial shifter has shifted out. The transmitter
finishes the transmission, then sends a preamble. After the preamble is transmitted, if
TDRE is set, the transmitter will mark idle. Otherwise, normal transmission of the next
sequence will begin.
Both TDRE and TC have associated interrupts. The interrupts are enabled by the
transmit interrupt enable (TIE) and transmission complete interrupt enable (TCIE) bits
in SCCR1. Service routines can load the last byte of data in a sequence into SCDR,
then terminate the transmission when a TDRE interrupt occurs.
The RE bit in SCCR1 enables (RE = 1) and disables (RE = 0) the receiver. The receiv-
er contains a receive serial shifter and a parallel receive data register (RDR) located
in the SCI data register (SCDR). The serial shifter cannot be directly accessed by the
CPU16. The receiver is double-buffered, allowing data to be held in the RDR while oth-
er data is shifted in.
Receiver bit processor logic drives a state machine that determines the logic level for
each bit-time. This state machine controls when the bit processor logic is to sample
the RXD pin and also controls when data is to be passed to the receive serial shifter.
MULTICHANNEL COMMUNICATION INTERFACE
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