MC68HC16Z1CEH16 Freescale Semiconductor, MC68HC16Z1CEH16 Datasheet - Page 493

• Manufacturer Part Number: MC68HC16Z1CEH16
• Description: IC MCU 16BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Processor Series: HC16Z
• Core: CPU16
• Data Bus Width: 16 bit
• Controller Family/series: 68HC16
• No. Of I/o's: 26
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

QSMCR
QSPI 9-1,
M68HC16 Z SERIES
USER’S MANUAL
registers
SCI
block diagram
command RAM
enable (SPE)
finished flag (SPIF)
initialization operation
loop mode (LOOPQ)
master operation flow
operating modes
operation
peripheral chip-selects
pins
RAM
registers
timing
9-21
command RAM (CR) D-52
global registers
module configuration register (QSMCR)
pin control registers
QSPI
receive data RAM (RR) D-51
SCI
test register (QTEST)
transmit data RAM (TR)
types
operation
pins
registers
D-38
master mode 9-9,
slave mode 9-9,
receive RAM
transmit RAM
control registers
status register
9-8
9-7
9-5
A-46
interrupt
test register (QTEST)
port QS
control register 0 (SPCR0)
control register 1 (SPCR1)
control register 2 (SPCR2)
control register 3 (SPCR3) D-50
status register (SPSR) D-50
control register 0 (SCCR0)
control register 1 (SCCR1)
data register (SCDR)
status register (SCSR)
wraparound mode
wraparound mode
9-25
9-6
9-8
9-2
level register (QILR) 9-2,
vector register (QIVR) 9-2,
data
data direction register (DDRQS)
data register (PORTQS)
pin assignment register (PQSPAR)
9-24
D-48
9-25
9-5
9-8
9-9
direction register (DDRQS)
register (PORTQS)
9-7
9-7
9-7
D-51
9-2
9-20
9-6
D-50
9-11
9-10
D-45
9-16
9-21
9-4
Freescale Semiconductor, Inc.
D-39
9-19
9-21
D-52
For More Information On This Product,
D-44
9-2
D-43
D-46
D-48
D-49
D-40
D-41
D-44
9-4
D-39
Go to: www.freescale.com
D-39
D-38
D-45
9-4
QTEST 9-2,
Queue pointers
Queued serial
R/W
RAF D-43,
RAM
RAMBAH/BAL 6-1,
RAMMCR 6-1,
RAMTST 6-1,
RASP 6-2,
RC
RDR
RDRF 9-28, 10-21, D-43,
RE 9-28, 10-4, 10-13, 10-20, D-42,
Read
Receive
Receiver
Register bit and field mnemonics
Relative addressing modes
RES10 8-7,
RESET 5-48, 5-50, 5-54,
Reset
completed queue pointer (CPTQP)
end queue pointer (ENDQP)
new queue pointer (NEWQP)
module (QSM). See QSM
peripheral interface (QSPI) See QSPI. 9-1,
field 5-66,
array space (RASP)
base address lock (RLCK) bit
encoding 6-2,
DAC array
low pass filter
/write signal (R/W)
cycle
data
RAM
time sample clock (RT) 9-26, 9-28, 10-18,
active (RAF) D-43,
data register (RDRF) flag 9-28,
enable (RE) 9-28, 10-4, 10-13, 10-20, D-42,
interrupt enable (RIE) D-42, D-61
wakeup (RWU) 9-30, 10-22, D-42,
and mode select timing
exception processing
module pin function out of reset 5-52
operation in SIM
power-on
5-32
9-24
— master, CPHA = 0/CPHA = 1
— slave, CPHA = 0/CPHA = 1
low voltage
timing diagram A-29
(RXD) pin — QSM
(RXDA/B) pins (MCCI)
register full (RDRF) D-43,
control logic
mode selection
9-7
5-37
D-63
D-23
D-31
D-39
D-24
5-55
D-19
D-23
8-5
D-23
8-16
D-24
A-45
5-48
5-48
5-32
D-63
5-49
D-23
–R–
5-55
D-63
5-48
4-10
9-25
A-36
9-1
10-17
2-3
9-8
9-8
D-23
D-63
D-62
10-21
D-62
A-48
9-8
A-47
10-21
9-5
D-62
I-11