MC68HC16Z1CEH16 Freescale Semiconductor, MC68HC16Z1CEH16 Datasheet - Page 271

IC MCU 16BIT 16MHZ 132-PQFP

MC68HC16Z1CEH16

Manufacturer Part Number
MC68HC16Z1CEH16
Description
IC MCU 16BIT 16MHZ 132-PQFP
Manufacturer
Freescale Semiconductor
Series
HC16r
Datasheets

Specifications of MC68HC16Z1CEH16

Core Processor
CPU16
Core Size
16-Bit
Speed
16MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
132-QFP
Processor Series
HC16Z
Core
CPU16
Data Bus Width
16 bit
Controller Family/series
68HC16
No. Of I/o's
26
Ram Memory Size
1KB
Cpu Speed
16MHz
No. Of Timers
2
Embedded Interface Type
QSPI, SCI
Rohs Compliant
Yes
Package
132PQFP
Family Name
HC16
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Number Of Programmable I/os
16
On-chip Adc
8-chx10-bit
Number Of Timers
11
Data Ram Size
1 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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11.5 Pin Descriptions
11.5.1 Input Capture Pins
11.5.2 Input Capture/Output Compare Pin
11.5.3 Output Compare Pins
11.5.4 Pulse Accumulator Input Pin
M68HC16 Z SERIES
USER’S MANUAL
Interrupt requests are asserted until associated status flags are cleared. Status flags
must be cleared in a particular sequence. The status register must first be read for set
flags, then zeros must be written to the flags that are to be cleared. If a new event oc-
curs between the time that the register is read and the time that it is written, the asso-
ciated flag is not cleared.
For more information on interrupts, refer to
exceptions, refer to
The GPT uses 12 of the MCU pins. Each pin can perform more than one function. De-
scriptions of GPT pins divided into functional groups follow.
Each input capture pin is associated with a single GPT input capture function. Each
pin has hysteresis. Any pulse longer than two system clocks is guaranteed to be valid
and any pulse shorter than one system clock is ignored. Each pin has an associated
16-bit capture register that holds the captured counter value. These pins can also be
used for general-purpose I/O. Refer to
formation.
The input capture/output compare pin can be configured for use by either an input cap-
ture or an output compare function. It has an associated 16-bit register that is used for
holding either the input capture value or the output match value. When used for input
capture the pin has the same hysteresis as other input capture pins. The pin can be
used for general-purpose I/O. Refer to
Output Compare Functions
Output compare pins are used for GPT output compare functions. Each pin has an as-
sociated 16-bit compare register and a 16-bit comparator. Pins OC2, OC3, and OC4
are associated with a specific output compare function. The OC1 function can affect
the output of all compare pins. If the OC1 pin is not needed for an output compare
function it can be used to output the clock selected for the timer counter register. Any
of these pins can also be used for general-purpose I/O. Refer to
pare Functions
The pulse accumulator input (PAI) pin connects a discrete signal to the pulse accumu-
lator for timed or gated pulse accumulation. PAI has hysteresis. Any pulse longer than
two system clocks is guaranteed to be valid and any pulse shorter than one system
clock is ignored. It can be used as a general-purpose input pin. Refer to
Accumulator
for more information.
for more information.
Freescale Semiconductor, Inc.
4.13.4 Types of
For More Information On This Product,
GENERAL-PURPOSE TIMER
Go to: www.freescale.com
for more information.
Exceptions.
11.8.2 Input Capture Functions
11.8.2 Input Capture Functions
5.8
Interrupts. For more information on
11.8.3 Output Com-
11.10 Pulse
for more in-
and
11.8.3
11-7

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