MC68HC16Z1CEH16 Freescale Semiconductor, MC68HC16Z1CEH16 Datasheet - Page 69

• Manufacturer Part Number: MC68HC16Z1CEH16
• Description: IC MCU 16BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Processor Series: HC16Z
• Core: CPU16
• Data Bus Width: 16 bit
• Controller Family/series: 68HC16
• No. Of I/o's: 26
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.6.1 Immediate Addressing Modes
M68HC16 Z SERIES
USER’S MANUAL
All modes generate ADDR[15:0]. This address is combined with ADDR[19:16] from an
operand or an extension field to form a 20-bit effective address.
In the immediate modes, an argument is contained in a byte or word immediately fol-
lowing the instruction. For IMM8 and IMM16 modes, the effective address is the ad-
dress of the argument.
There are three specialized forms of IMM8 addressing.
• The AIS, AIX, AIY, AIZ, ADDD, and ADDE instructions decrease execution time
• The MAC and RMAC instructions use an 8-bit immediate operand to specify two
• The PSHM and PULM instructions use an 8-bit immediate mask operand to indi-
by sign-extending the 8-bit immediate operand to 16 bits, then adding it to an ap-
propriate register.
signed 4-bit index register offsets.
cate which registers must be pushed to or pulled from the stack.
Post-Modified Index
Accumulator Offset
Access across 64-Kbyte address boundaries is transparent. AD-
DR[19:16] of the effective address are changed to make an access
across a bank boundary. Extension field values will not change as a
result of effective address computation.
Indexed 16-Bit
Indexed 20-Bit
Indexed 8-Bit
Immediate
Extended
Inherent
Relative
Mode
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 4-1 Addressing Modes
CENTRAL PROCESSOR UNIT
Mnemonic
Go to: www.freescale.com
IND16, X
IND16, Y
IND16, Z
IND20, X
IND20, Y
IND20, Z
IND8, X
IND8, Y
IND8, Z
EXT20
IMM16
REL16
IMM8
REL8
EXT
INH
E,X
E,Y
E,Z
IXP
NOTE
Index register X with accumulator E offset
Index register Y with accumulator E offset
Index register Z with accumulator E offset
Extended
20-bit extended
8-bit immediate
16-bit immediate
Index register X with unsigned 8-bit offset
Index register Y with unsigned 8-bit offset
Index register Z with unsigned 8-bit offset
Index register X with signed 16-bit offset
Index register Y with signed 16-bit offset
Index register Z with signed 16-bit offset
Index register X with signed 20-bit offset
Index register Y with signed 20-bit offset
Index register Z with signed 20-bit offset
Inherent
Signed 8-bit offset added to index register
X after effective address is used
8-bit relative
16-bit relative
Description
4-9