MC68HC705B16CFN Freescale Semiconductor, MC68HC705B16CFN Datasheet - Page 107

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MC68HC705B16CFN

Manufacturer Part Number
MC68HC705B16CFN
Description
IC MCU 2.1MHZ 15K OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705B16CFN

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
15KB (15K x 8)
Program Memory Type
OTP
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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9.1.3
When the oscillator is running in a stable condition, the MCU is reset when a logic zero is applied
to the RESET input for a minimum period of 1.5 machine cycles (t
is used to improve noise immunity on this pin. When the RESET pin goes high, the MCU will
resume operation on the following cycle. When a reset condition occurs internally, i.e. from POR
or the COP watchdog, the RESET pin provides an active-low open drain output signal which may
be used to reset external hardware. Current limitation to protect the pull-down device is provided
in case an RC type external reset circuit is used.
9.1.4
The watchdog counter system consists of a divide-by-8 counter, preceded by a fixed divide-by-4
and a fixed divide-by-256 prescaler, plus control logic as shown in
counter can be reset by software.
Warning: The input to the watchdog system is derived from the carry output of bit 7 of the free
The watchdog system can be automatically enabled, following power-on or external reset, via a
mask option (see
in the miscellaneous register at $000C (see
MC68HC05B6
Rev. 4.1
f
f
OSC
OSC
Main CPU
clock
/32
/2
prescaler
running timer counter. Therefore, a reset of the timer may affect the period of the
watchdog timeout.
÷ 4
RESET pin
Computer operating properly (COP) watchdog reset
Section
running counter)
(Bit 7 of free
Figure 9-2 Watchdog system block diagram
WDOG bit
÷ 256
1.2), or it can be enabled by software by writing a ‘1’ to the WDOG bit
RESETS AND INTERRUPTS
÷ 8 watchdog
Control logic
counter
Section
9.1.2). Once enabled, the watchdog system
R
S
Schmitt
trigger
Latch
CYC
). An internal Schmitt Trigger
Figure
protection
Power-on
Input
9-2. The divide-by-8
Freescale
Reset
pin
9-3
9

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