MC68HC705B16CFN Freescale Semiconductor, MC68HC705B16CFN Datasheet - Page 55

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MC68HC705B16CFN

Manufacturer Part Number
MC68HC705B16CFN
Description
IC MCU 2.1MHZ 15K OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705B16CFN

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
15KB (15K x 8)
Program Memory Type
OTP
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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4.3
In addition to the standard port functions described for port A and B, port C pin 2 can be
configured, using the ECLK bit of the EEPROM/ECLK control register, to output the CPU clock. If
this is selected the corresponding DDR bit is automatically set and bit 2 of port C will always read
the output data latch. The other port C pins are not affected by this feature.
ECLK — External clock output bit
The ECLK bit is cleared by power-on or external reset. It is not affected by the execution of a STOP
or WAIT instruction.
The timing diagram of the clock output is shown in
4.4
This 8-bit input-only port shares its pins with the A/D converter subsystem. When the A/D
converter is enabled, pins PD0-PD7 read the eight analog inputs to the A/D converter. Port D can
be read at any time, however, if it is read during an A/D conversion sequence noise, may be
injected on the analog inputs, resulting in reduced accuracy of the A/D. Furthermore, performing
MC68HC05B6
Rev. 4.1
EEPROM/ECLK control
1 (set)
0 (clear) –
Internal clock (PHI2)
External clock (ECLK/PC2)
Output port (if write to output port)
Port C
Port D
ECLK CPU clock is output on PC2.
ECLK CPU clock is not output on PC2; port C acts as a normal I/O port.
Address
$0007
Figure 4-2 ECLK timing diagram
INPUT/OUTPUT PORTS
bit 7
0
bit 6
0
bit 5
Figure
0
bit 4
4-2.
0
ECLK E1ERA E1LAT E1PGM 0000 0000
bit 3
bit 2
bit 1
bit 0
Freescale
on reset
State
4-3
4

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