MC68HC705B16CFN Freescale Semiconductor, MC68HC705B16CFN Datasheet - Page 65

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MC68HC705B16CFN

Manufacturer Part Number
MC68HC705B16CFN
Description
IC MCU 2.1MHZ 15K OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705B16CFN

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
15KB (15K x 8)
Program Memory Type
OTP
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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ICF2 — Input capture flag 2
This bit is set when a negative edge is detected by the input capture edge detector 2 at TCAP2;
an input capture interrupt will be generated if ICIE is set. ICF2 is cleared by reading the TSR and
then the input capture low register 2 ($1D).
OCF2 — Output compare flag 2
This bit is set when the output compare 2 register contents match those of the free-running
counter; an output compare interrupt will be generated if OCIE is set. OCF2 is cleared by reading
the TSR and then reading or writing the output compare 2 low register ($1F).
5.3
‘Input capture’ is a technique whereby an external signal is used to trigger a read of the free
running counter. In this way it is possible to relate the timing of an external signal to the internal
counter value, and hence to elapsed time.
There are two input capture registers: input capture register 1 (ICR1) and input capture register 2 (ICR2).
The same input capture interrupt enable bit (ICIE) is used for the two input captures.
5.3.1
The two 8-bit registers that make up the 16-bit input capture register 1 are read-only, and are used
to latch the value of the free-running counter after the input capture edge detector circuit 1 senses
a valid transition at TCAP1. The level transition that triggers the counter transfer is defined by the
input edge bit (IEDG1). When an input capture 1 occurs, the corresponding flag ICF1 in TSR is
set. An interrupt can also accompany an input capture 1 provided the ICIE bit in TCR is set. The
8 most significant bits are stored in the input capture high 1 register at $14, the 8 least significant
bits in the input capture low 1 register at $15.
MC68HC05B6
Rev. 4.1
Input capture high 1
1 (set)
0 (clear) –
1 (set)
0 (clear) –
Input capture low 1
Input capture
Input capture register 1 (ICR1)
A valid (negative) input capture has occurred.
No input capture has occurred.
A valid output compare has occurred.
No output compare has occurred.
Address
$0014
$0015
PROGRAMMABLE TIMER
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Freescale
Undefined
Undefined
on reset
State
5-7
5

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