MC68HC705B16CFN Freescale Semiconductor, MC68HC705B16CFN Datasheet - Page 128

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MC68HC705B16CFN

Manufacturer Part Number
MC68HC705B16CFN
Description
IC MCU 2.1MHZ 15K OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705B16CFN

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
15KB (15K x 8)
Program Memory Type
OTP
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
10
10.3.4
In the extended addressing mode, the effective address of the argument is contained in the two
bytes following the opcode byte. Instructions with extended addressing mode are capable of
referencing arguments anywhere in memory with a single three-byte instruction. When using the
Freescale assembler, the user need not specify whether an instruction uses direct or extended
addressing. The assembler automatically selects the short form of the instruction.
10.3.5
In the indexed, no offset addressing mode, the effective address of the argument is contained in
the 8-bit index register. This addressing mode can access the first 256 memory locations. These
instructions are only one byte long. This mode is often used to move a pointer through a table or
to hold the address of a frequently referenced RAM or I/O location.
10.3.6
In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of
the unsigned 8-bit index register and the unsigned byte following the opcode. Therefore the
operand can be located anywhere within the lowest 511 memory locations. This addressing mode
is useful for selecting the mth element in an n element table.
10.3.7
In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of
the unsigned 8-bit index register and the two unsigned bytes following the opcode. This address
mode can be used in a manner similar to indexed, 8-bit offset except that this three-byte instruction
allows tables to be anywhere in memory. As with direct and extended addressing, the Freescale
assembler determines the shortest form of indexed addressing.
Freescale
10-12
Extended
Indexed, no offset
Indexed, 8-bit offset
Indexed, 16-bit offset
Address bus high ← (PC+1)+K; Address bus low ← X+(PC+2)
Address bus high ← (PC+1); Address bus low ← (PC+2)
where K = the carry from the addition of X and (PC+1)
where K = the carry from the addition of X and (PC+2)
Address bus high ← K; Address bus low ← X+(PC+1)
Address bus high ← 0; Address bus low ← X
CPU CORE AND INSTRUCTION SET
EA = X+[(PC+1):(PC+2)]; PC ← PC+3
EA = (PC+1):(PC+2); PC ← PC+3
EA = X+(PC+1); PC ← PC+2
EA = X; PC ← PC+1
MC68HC05B6
Rev. 4.1

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