MC68HC705B16CFN Freescale Semiconductor, MC68HC705B16CFN Datasheet - Page 263

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MC68HC705B16CFN

Manufacturer Part Number
MC68HC705B16CFN
Description
IC MCU 2.1MHZ 15K OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705B16CFN

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
15KB (15K x 8)
Program Memory Type
OTP
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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H.5
Oscillator divide-by-two is forced in bootstrap mode.
The 432 bytes of self-check firmware on the MC68HC05B6 are replaced by 654 bytes of bootstrap
firmware. A detailed description of the modes of operation within bootstrap mode is given below.
The bootstrap program in mask ROM address locations $0200 to $024F, $03B0 to $3FFF, $7E00
to $7FDD and $7FE0 to $7FEF can be used to program the EPROM and the EEPROM, to check
if the EPROM is erased or to load and execute data in RAM.
After reset, while going to the bootstrap mode, the vector located at address $7FEE and $7FEF
(RESET) is fetched to start execution of the bootstrap program. To place the part in bootstrap
mode, the IRQ pin should be at 2xV
pin from low to high. The hold time on the IRQ and TCAP1 pins is two clock cycles after the
external RESET pin is brought high.
When the MC68HC705B32 is placed in the bootstrap mode, the bootstrap reset vector will be
fetched and the bootstrap firmware will start to execute.
to enter each level of bootstrap mode on the rising edge of RESET.
The bootstrap program will first copy part of itself in RAM (except ‘RAM parallel load’), as the
program cannot be executed in ROM during verification/programming of the EPROM. It will then
set the TCMP1 output to a logic high level, unlike the MC68HC05B6 which keeps TCMP1 low. This
can be used to distinguish between the two circuits and, in particular, for selection of the VPP level
and current capability.
MC68HC05B6
Rev. 4.1
x = Don’t care
V
IRQ pin
SS
2xV
2xV
2xV
2xV
2xV
2xV
2xV
to V
DD
DD
DD
DD
DD
DD
DD
DD
TCAP1 pin PD1 PD2 PD3 PD4
V
Bootstrap mode
SS
V
V
V
V
V
V
V
to V
DD
DD
DD
DD
DD
DD
DD
DD
x
0
1
0
1
x
0
x
Table H-4 Mode of operation selection
x
0
0
1
1
1
1
x
0
0
0
0
1
0
1
x
DD
with the TCAP1 pin ‘high’ during transition of the RESET
0
0
0
0
1
1
MC68HC705B32
x
x
Single chip
Erased EPROM verification
EPROM verification; erase EEPROM;
EPROM/EEPROM parallel program/verify
Erased EPROM verification;
no EEPROM erase if SEC is zero (parallel mode)
Erased EPROM verification; erase EEPROM;
EPROM parallel program/verify (no E
Jump to start of RAM ($0051); SEC bit = ACTIVE
EPROM and EEPROM verification; SEC bit = ACTIVE (parallel mode)
Serial RAM load/execute – similar to MC68HC05B6 but can fill RAM I,
II and III
Table H-4
shows the conditions required
Mode
2
)
Freescale
H-13
14

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