MC68HC705B16CFN Freescale Semiconductor, MC68HC705B16CFN Datasheet - Page 34
Manufacturer Part Number
IC MCU 2.1MHZ 15K OTP 52-PLCC
Specifications of MC68HC705B16CFN
Number Of I /o
Program Memory Size
15KB (15K x 8)
Program Memory Type
256 x 8
352 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
-40°C ~ 85°C
Package / Case
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
The STOP and WAIT instructions have different effects on the programmable timer, the serial
communications interface, the watchdog system, the EEPROM and the A/D converter. These
different effects are described in the following sections.
The STOP instruction places the MCU in its lowest power consumption mode. In STOP mode, the
internal oscillator is turned off, halting all internal processing including timer, serial
communications interface and the A/D converter (see flowchart in
the MCU to wake-up from the STOP mode is by receipt of an external interrupt or by the detection
of a reset (logic low on RESET pin or a power-on reset).
During STOP mode, the I-bit in the CCR is cleared to enable external interrupts (see
while exiting STOP mode (see
All other registers and memory remain unaltered and all input/output lines remain unchanged.
This continues until an external interrupt (IRQ) or reset is sensed, at which time the internal
oscillator is turned on. The external interrupt or reset causes the program counter to vector to the
corresponding locations ($1FFA, B and $1FFE, F respectively).
When leaving STOP mode, a t
stabilise before releasing CPU operation. This delay is selectable via a mask option to be either
16 or 4064 cycles. The CPU will resume operation by servicing the interrupt that wakes it up, or
by fetching the reset vector, if reset wakes it up.
Warning: If t
The following list summarizes the effect of STOP mode on the individual modules of the
– The watchdog timer is reset; refer to
– The EEPROM acts as read-only memory (ROM); refer to
– All SCI activity stopped; refer to
– The timer stops counting; refer to
– The PLM outputs remain at current level; refer to
– The A/D converter is disabled; refer to
– The I-bit in the CCR is cleared
10.1.5). The SM bit is cleared to allow nominal speed operation for the 4064 cycles count
used to avoid problems with oscillator stability while the device is in STOP mode.
The stacking corresponding to an eventual interrupt to go out of STOP mode will only
be executed when going out of STOP mode.
Low power modes
is selected to be 16 cycles, it is recommended that an external clock signal is
MODES OF OPERATION AND PIN DESCRIPTIONS
internal cycles delay is provided to give the oscillator time to
2-3). The only way for