MC68HC705B16CFN Freescale Semiconductor, MC68HC705B16CFN Datasheet - Page 291

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MC68HC705B16CFN

Manufacturer Part Number
MC68HC705B16CFN
Description
IC MCU 2.1MHZ 15K OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705B16CFN

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
15KB (15K x 8)
Program Memory Type
OTP
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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A
A/D converter
A/D converter characteristics
A/D status/control register
absolute maximum ratings
ADDATA – A/D result data register
ADON – A/D converter on
ADON – A/D converter on bit
ADRC – A/D RC oscillator control
ADSTAT
ADSTAT – A/D status/control register
alternate counter register
analog input
B
Baud rate register
block diagrams
In this index numeric entries are placed first; page references in italics indicate that the reference
is to a figure.
MC68HC05B6
block diagram
during STOP mode
during WAIT mode
operation
registers
ADON
ADON
ADRC
CH3-CH0
COCO
SCP1, SCP0
SCR2, SCR1, SCR0
SCT2, SCT1, SCT0
MC68HC05B16
MC68HC05B32
MC68HC05B4
MC68HC05B8
MC68HC705B16
MC68HC705B16N
ADDATA
ADSTAT
PORTD
8–4
4–5
8–5
8–4
F–22
8–6
8–1
8–5
,
8–3
6–18
8–4
8–3
8–2
F–23
A–2
B–2
D–3
G–2
E–2
F–2
8–6
8–6
,
6–18
5–3
6–19
H–25
8–5
11–1
11–8
4–5
,
H–26
8–4
,
8–3
11–9
8–4
,
I–3
,
E–24
,
E–25
INDEX
,
INDEX
bootstrap mode
C
ceramic resonator
CH3-CH0 – A/D channels 3, 2, 1 and 0
COCO – Conversion complete flag
control timing
COP watchdog
counter
counter register
CPHA – Clock phase
CPOL – Clock polarity 6–12
crystal
D
data direction registers
data format
DC electrical characteristics
E
E1ERA – EEPROM erase/programming bit
E1LAT – EEPROM programming latch enable
E1LAT – EEPROM programming latch enable bit
MC68HC705B32
MC68HC705B5
PLM system
programmable timer
SCI
watchdog system
during STOP mode
during WAIT mode
DDRA, DDRB, DDRC
2–11
5–1
6–2
6–5
F–25
E–23
F–7
F–7
,
11–10
6–2
9–3
C–8
5–3
,
,
7–1
,
,
H–9
H–10
2–11
H–27
F–20
,
,
C–2
11–11
6–12
H–4
E–10
9–3
9–4
9–4
,
,
5–2
F–21
H–28
4–5
,
,
11–2
H–12
C–19
,
,
,
H–23
I–4
,
8–4
11–5
E–26
,
8–5
,
H–24
,
C–19
3–3
E–27
Freescale
,
3–4
,
,
I–2
E–7
,
E–7
E–22
F–24
,
,
,
,
v

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