MC68HC705B16CFN Freescale Semiconductor, MC68HC705B16CFN Datasheet - Page 57

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MC68HC705B16CFN

Manufacturer Part Number
MC68HC705B16CFN
Description
IC MCU 2.1MHZ 15K OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705B16CFN

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
15KB (15K x 8)
Program Memory Type
OTP
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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4.5.3
All the port D bits are input-only and are shared with the A/D converter. The function of each bit is
determined by the ADON bit in the A/D status/control register.
The state of the port data registers following reset is not defined.
4.5.3.1
ADON — A/D converter on
Reset clears the ADON bit, thus configuring port D as an input only port.
4.5.4
Writing a ‘1’ to any bit configures the corresponding port pin as an output; conversely, writing any
bit to ‘0’ configures the corresponding port pin as an input.
Reset clears these registers, thus configuring all ports as inputs.
MC68HC05B6
Rev. 4.1
Port C data direction (DDRC)
Port A data direction (DDRA)
Port B data direction (DDRB)
Port D data (PORTD)
1 (set)
0 (clear) –
A/D status/control
Port data register D (PORTD)
A/D status/control register
Data direction registers (DDRA, DDRB and DDRC)
A/D converter is switched on; all port D pins act as analog inputs for
the A/D converter.
A/D converter is switched off; all port D pins act as input only pins.
Address
Address
Address
$0003
$0009
$0004
$0005
$0006
INPUT/OUTPUT PORTS
COCO ADRC ADON
bit 7
PD7
bit 7
bit 7
bit 6
PD6
bit 6
bit 6
PD5
bit 5
bit 5
bit 5
bit 4
PD4
bit 4
bit 4
0
PD3
CH3
bit 3
bit 3
bit 3
bit 2
PD2
bit 2
CH2
bit 2
PD1
CH1
bit 1
bit 1
bit 1
bit 0
PD0
bit 0
CH0
bit 0
Freescale
0000 0000
0000 0000
0000 0000
0000 0000
Undefined
on reset
on reset
on reset
State
State
State
4-5
4

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