MC68HC705B16CFN Freescale Semiconductor, MC68HC705B16CFN Datasheet - Page 52

no-image

MC68HC705B16CFN

Manufacturer Part Number
MC68HC705B16CFN
Description
IC MCU 2.1MHZ 15K OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705B16CFN

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
15KB (15K x 8)
Program Memory Type
OTP
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC705B16CFN
Manufacturer:
MOT
Quantity:
5 510
Part Number:
MC68HC705B16CFN
Manufacturer:
MOT
Quantity:
2 132
Company:
Part Number:
MC68HC705B16CFN
Manufacturer:
MOI
Quantity:
1 000
Part Number:
MC68HC705B16CFN
Manufacturer:
FREESCALE
Quantity:
1 402
Part Number:
MC68HC705B16CFNE
Manufacturer:
FREESCALE
Quantity:
2 512
3
SFA — Slow or fast mode selection for PLMA (see
This bit allows the user to select the slow or fast mode of the PLMA pulse length modulation
output.
SFB — Slow or fast mode selection for PLMB (see
This bit allows the user to select the slow or fast mode of the PLMB pulse length modulation
output.
Note:
Warning: Because the SFA bit and SFB bit are not double buffered, it is mandatory to set the SFA
SM — Slow mode (see
The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when
entering STOP mode.
WDOG — Watchdog enable/disable (see
The WDOG bit can be used to enable the watchdog timer previously disabled by a mask option.
Following a watchdog reset the state of the WDOG bit is as defined by the mask option specified.
Once the watchdog is enabled, the WDOG bit acts as a reset mechanism for the watchdog
counter. Writing a’1’ to this bit clears the counter to its initial value and prevents a watchdog
timeout.
Freescale
3-10
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
The highest speed of the PLM system corresponds to the frequency of the TOF bit
being set, multiplied by 256. The lowest speed of the PLM system corresponds to the
frequency of the TOF bit being set, multiplied by 16.
bit and SFB bit to the desired values before writing to the PLM registers; not doing so
could temporarily give incorrect values at the PLM outputs.
Slow mode PLMA (4096 x timer clock period).
Fast mode PLMA (256 x timer clock period).
Slow mode PLMB (4096 x timer clock period).
Fast mode PLMB (256 x timer clock period).
The system runs at a bus speed 16 times lower than normal
(f
SCI, A/D and timer.
The system runs at normal bus speed (f
Watchdog counter cleared and enabled.
The watchdog cannot be disabled by software; writing a zero to this
bit has no effect.
OSC
Section
/32). SLOW mode affects all sections of the device, including
2.4.3)
MEMORY AND REGISTERS
Section
9.1.4)
Section
Section
OSC
7.1)
7.1)
/2).
MC68HC05B6
Rev. 4.1

Related parts for MC68HC705B16CFN