MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 187
![IC MPU QUICC 25MHZ 240-FQFP](/photos/39/60/396094/4532975_sml.jpg)
MC68EN360CAI25L
Manufacturer Part Number
MC68EN360CAI25L
Description
IC MPU QUICC 25MHZ 240-FQFP
Manufacturer
Freescale Semiconductor
Series
MC68000r
Datasheets
1.MC68EN302AG20BT.pdf
(8 pages)
2.MC68EN360VR25L.pdf
(14 pages)
3.MC68EN360VR25L.pdf
(2 pages)
4.MC68EN360CAI25L.pdf
(962 pages)
Specifications of MC68EN360CAI25L
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Core Size
32 Bit
Cpu Speed
25MHz
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
FQFP
No. Of Pins
240
Supply Voltage Range
4.75V To 5.25V
Rohs Compliant
Yes
Family Name
M68xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
240
Package Type
FQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68EN360CAI25L
Manufacturer:
APLHA
Quantity:
12 000
Company:
Part Number:
MC68EN360CAI25L
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68EN360CAI25L
Manufacturer:
FREESCALE
Quantity:
20 000
- MC68EN302AG20BT PDF datasheet
- MC68EN360VR25L PDF datasheet #2
- MC68EN360VR25L PDF datasheet #3
- MC68EN360CAI25L PDF datasheet #4
- Current page: 187 of 962
- Download datasheet (4Mb)
Exception processing for privilege violations is nearly identical to that for illegal instructions.
The instruction is fetched and decoded. If the processor determines that a privilege violation
has occurred, exception processing begins before instruction execution.
Exception processing follows the regular sequence. The vector number (8) is generated to
reference the privilege violation vector. Privilege violation vector offset, current PC, and SR
are saved on the supervisor stack. The saved PC value is the address of the first word of
the instruction causing the privilege violation.
5.5.2.10 TRACING. To aid in program development, M68000 processors include a facility
to allow tracing of instruction execution. CPU32+ tracing also has the ability to trap on
changes in program flow. In trace mode, a trace exception is generated after each instruc-
tion executes, allowing a debugging program to monitor the execution of a program under
test. The T1 and T0 bits in the supervisor portion of the SR are used to control tracing.
When T1–T0 = 00, tracing is disabled, and instruction execution proceeds normally (see
Table 5-18).
When T1–T0 = 01 at the beginning of instruction execution, a trace exception will be gener-
ated if the PC changes sequence during execution. All branches, jumps, subroutine calls,
returns, and SR manipulations can be traced in this way. No exception occurs if a branch is
not taken.
When T1–T0 = 10 at the beginning of instruction execution, a trace exception will be gener-
ated when execution is complete. If the instruction is not executed, either because an inter-
rupt is taken or because the instruction is illegal, unimplemented, or privileged, an exception
is not generated.
• MOVE to SR
• MOVE USP
• MOVEC
• MOVES
• OR Immediate to SR
• RESET
• RTE
• STOP
Freescale Semiconductor, Inc.
For More Information On This Product,
T1
0
0
1
1
Table 5-18. Tracing Control
MC68360 USER’S MANUAL
Go to: www.freescale.com
T0
0
1
0
1
No tracing
Trace on change of flow
Trace on instruction execution
Undefined; reserved
Tracing Function
CPU32+
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