MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 287

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

RRQEN—RISC Request Enable
DFNL—Division Factor Lowest Frequency
DFNH—Division Factor High Frequency
CSRC—Clock Source Bit
This bit specifies if the general system clock returns to high frequency (defined by the
DFNH bits) while the CPM RISC controller is not idle.
These bits are required in two cases: 1) to reduce the general system clock to a frequency
lower than that which can be obtained in DFNH and 2) to automatically switch between
the DFNL rate and the DFNH rate. See 6.5.5 QUICC Internal Clock Signals for details on
how to automatically switch between the DFNH rate and the DFNL rate.
The user may load these bits with the desired divide value, and then set the CSRC bit to
change the frequency. Changing the value of the these bits will never cause a loss-of-lock
condition. These bits are cleared by a hardware reset.
Changing the value of these bits will never cause a loss-of-lock condition. These bits are
cleared (divide by 1) by a hardware reset. The default value is divide by 1 (VCO/2), which
is 25 MHz in a 25-MHz system. The user may write the DFNH bits at any time to change
the general system clock rate.
See 6.5.5 QUICC Internal Clock Signals for details on how to automatically switch be-
tween the DFNH rate and the DFNL rate.
The CSRC bit specifies whether the general system clock is determined by the DFNH or
the DFNL bits. Setting this bit switches the general system clock to the DFNL value (i.e.,
0 = Remain in lower frequency (defined by DFNL) even if the RISC controller is not
1 = Switch to the high frequency (defined by DFNH) when the RISC controller needs
000 = Divide by 2
001 = Divide by 4
010 = Divide by 8
011 = Divide by 16
100 = Divide by 32
101 = Divide by 64
110 = Reserved
111 = Divide by 256
000 = Divide by 1 (normal operation of general system clock when CSRC = 0)
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
110 = Divide by 64
111 = Reserved
idle.
to execute a routine.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
System Integration Module (SIM60)