MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 481

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

FLC—Flow Control
SL—Stop Length
CL—Character Length
UM—UART Mode
The SL bit selects the number of the stop bits transmitted by the UART. This bit may be
modified on the fly. The receiver is always enabled for one stop bit unless the UART is in
synchronous mode and the RZS bit is set. Fractional stop bits are configured in the DSR.
The CL bits determine the number of data bits in the character, not including the optional
parity or multidrop address bits. When less than an 8-bit character is used, the MSBs in
memory are written as zeros, and on transmission the MSBs in memory are a don’t care.
These bits may be modified on the fly.
The UART mode bits select the protocol that is implemented over the ASYNC channel.
These bits may be modified on the fly.
0 = Normal operation. The GSMR and port C registers determine the mode of the CTS
1 = Asynchronous flow control. When the CTS pin is negated, the transmitter will stop
0 = One Stop Bit
1 = Two Stop Bits
00 = 5 Data Bits
01 = 6 Data Bits
10 = 7 Data Bits
11 = 8 Data Bits
00 = Normal UART operation. Multidrop mode is disabled, and an idle-line wake-up is
01 = Multidrop non-automatic mode. In the multidrop mode, an additional address/data
10 = Reserved
11 = Multidrop automatic mode. In this mode, the CP automatically checks the address
pin.
transmitting at the end of the current character. (If CTS is negated past the middle
of the current character, the next full character may be sent, and then transmission
will be stopped.) When CTS is asserted once more, transmission will continue
where it left off. No CTS lost error will be reported. No characters except idles will
be transmitted while CTS is negated.
selected. In the idle-line wake-up mode, the UART receiver is reenabled by re-
ceiving one character of all ones.
bit is transmitted with each character. The multidrop asynchronous modes are
compatible with the MC68681 DUART, the MC68HC11 SCI, the DSP56000 SCI,
and the Intel 8051 serial interface. The UART receiver is reenabled when the last
data bit received in the character (i.e., the address bit) is a one. This means that
the received character is an address that has to be processed by all inactive pro-
cessors. The UART receives the address character and writes it to a new buffer.
The CPU32+ core then compares the written address with its own address to de-
cide whether to ignore or process the following characters.
of the incoming address character using the UADDR1 and UADDR2 parameter
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Serial Communication Controllers (SCCs)