MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 191

IC MPU QUICC 25MHZ 240-FQFP

MC68EN360CAI25L

Manufacturer Part Number
MC68EN360CAI25L
Description
IC MPU QUICC 25MHZ 240-FQFP
Manufacturer
Freescale Semiconductor
Series
MC68000r

Specifications of MC68EN360CAI25L

Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Core Size
32 Bit
Cpu Speed
25MHz
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
FQFP
No. Of Pins
240
Supply Voltage Range
4.75V To 5.25V
Rohs Compliant
Yes
Family Name
M68xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
240
Package Type
FQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68EN360CAI25L
Manufacturer:
APLHA
Quantity:
12 000
Part Number:
MC68EN360CAI25L
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68EN360CAI25L
Manufacturer:
FREESCALE
Quantity:
20 000
TP—BERR Frame Type
MV—MOVEM in Progress
SZC1,SCZ0—Original Operand Size
TR—Trace Pending
B1—Breakpoint Channel 1 Pending
B0—Breakpoint Channel 0 Pending
The TP field defines the class of the faulted bus operation. Two bus error exception frame
types are defined. One is for faults on prefetch and operand accesses, and the other is
for faults during exception frame stacking.
MV is set when the operand transfer portion of the MOVEM instruction is in progress at
the time of a bus fault. If a prefetch bus fault occurs while prefetching the MOVEM opcode
and extension word, both the MV and IN bits will be set.
The SZC1,SZC0 field specifies the size of the original bus cycle (i.e., the size bits of the
first cycle, when a transaction is divided into two or three cycles due to bus size or operand
address).
TR indicates that a trace exception was pending when a bus error exception was pro-
cessed. The instruction that generated the trace will not be restarted upon return from the
exception handler. This includes MOVEM and released write bus errors indicated by the
assertion of either MV or RR in the SSW.
B1 indicates that a breakpoint exception was pending on channel 1 (external breakpoint
source) when a bus error exception was processed. Pending breakpoint status is stacked,
regardless of the type of bus error exception.
B0 indicates that a breakpoint exception was pending on channel 0 (internal breakpoint
source) when the bus error exception was processed. Pending breakpoint status is
stacked, regardless of the type of bus error exception.
0 = Operand or prefetch bus fault
1 = Exception processing bus fault
0 = MOVEM was not in progress when fault occurred
1 = MOVEM was in progress when fault occurred
00 = Original operand size was long word
01 = Original operand size was byte
10 = Original operand size was word
11 = Unused, reserved
0 = Trace not pending
1 = Trace pending
0 = Breakpoint not pending
1 = Breakpoint pending
0 = Breakpoint not pending
1 = Breakpoint pending
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
CPU32+

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