MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 411

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7.8.5.4 SI COMMAND REGISTER (SICMR). The 8-bit SICMR allows the user to dynami-
cally program the SI RAM. For more information about dynamic programming, refer to
7.8.4.7 SI RAM Dynamic Changes
The contents of this register are valid only in the RAM division mode (RDM1–RDM0 bits in
SIGMR equal 01 or 11). This register is cleared at reset.
CSRRx—Change Shadow RAM for TDM A or B Receiver
CSRTx—Change Shadow RAM for TDM A or B Transmitter
Bits 3–0—Reserved
7.8.5.5 SI STATUS REGISTER (SISTR). The 8-bit SISTR indicates to the user which part
of the SI RAM is the current-route RAM. The value of this register is valid only when the cor-
responding bit in the SIGMR is clear. This register is cleared at reset.
CRORa—Current Route of TDMa Receiver
When set, this bit will cause the SI receiver to replace the current route with the shadow
RAM. The bit is set by the user and cleared by the SI.
When set, this bit will cause the SI transmitter to replace the current route with the shadow
RAM. The bit is set by the user and cleared by the SI.
These bits should be set to zero by the user.
0 = The receiver shadow RAM is not valid. The user can write into the shadow RAM to
1 = The receiver shadow RAM is valid. The SI will exchange between the RAMs and
0 = The transmitter shadow RAM is not valid. The user can write into the shadow RAM
1 = The transmitter shadow RAM is valid. The SI will exchange between the RAMs and
0 = The current-route receiver RAM is in address:
1 = The current route receiver RAM is in address:
program a new routing.
take the new receive routing from the receiver shadow RAM. This bit is cleared as
soon as the switch has completed.
to program a new routing.
take the new transmitter routing from the receiver shadow RAM. This bit is cleared
as soon as the switch has completed.
0–63 when the SI supports one TDM (RDM = 01)
0–31 when the SI supports two TDMs (RDM = 11)
64–127 when the SI supports one TDM (RDM = 01)
32–63 when the SI supports two TDMs (RDM = 11)
CSRRa
CRORa
Freescale Semiconductor, Inc.
7
7
For More Information On This Product,
CSRTa
CROTa
6
6
MC68360 USER’S MANUAL
Go to: www.freescale.com
CSRRb
CRORb
5
5
CSRTb
CROTb
4
4
3
3
2
2
Serial Interface with Time Slot Assigner
—
—
1
1
0
0