MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 565

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
Serial Communication Controllers (SCCs)
In addition, the QUICC has additional pins used to interface to an optional external content-
addressable memory (CAM). These pins are described in 7.10.23.7 CAM Interface.
External to the EEST are the passive components (principally transformers) required to con-
nect to AUI or twisted-pair media. For more information on the EEST connection circuits,
refer to the MC68160 device description.
The QUICC stores every byte received after the start frame delimiter into system memory,
using the SDMA channels. On transmit, the user provides the destination address, source
address, type/length field, and the transmit data. The QUICC will automatically pad frames
that have less than 46 bytes in the data field to meet the minimum frame requirements. In
addition, the QUICC will append the FCS to the frame.
7.10.23.5 ETHERNET CHANNEL FRAME TRANSMISSION. The Ethernet transmitter is
designed to work with almost no intervention from the host. When the host enables the
transmitter, the Ethernet controller will poll the first Tx BD in the channel’s Tx BD table. The
poll occurs every 128 serial clocks. If the user has a frame ready to transmit, the TOD bit in
the transmit-on-demand register may be set to eliminate waiting for the next poll to occur.
When there is a frame to transmit, the Ethernet controller will begin fetching the data from
the data buffer, assert TENA to the EEST, and start transmitting the preamble sequence,
the start frame delimiter, and then the frame information. However, the controller will defer
the transmission if the line is busy (carrier sense is active). Before transmitting, the controller
waits for carrier sense to become inactive. Once carrier sense becomes inactive, the con-
troller determines if carrier sense stays inactive for 6.0 s. If so, then the transmission will
begin after waiting an additional 3.6 s (i.e., 9.6 s after carrier sense originally became
inactive).
If a collision occurs during the transmit frame, the Ethernet controller follows the specified
backoff procedures and attempts to retransmit the frame until the retry limit threshold is
reached. The Ethernet controller stores the first 5 to 8 bytes of the transmit frame (8 bytes
if the transmit frame was long-word aligned) in internal RAM, so that they do not have to be
retrieved from system memory in case of a collision. This improves bus utilization and
latency in the case that the backoff timer output results in a need for an immediate retrans-
mission. If a collision occurs during the transmission of the frame, the Ethernet controller will
return to the first buffer for a retransmission. The only restriction is that the first buffer should
contain at least 9 bytes.
When the end of the current BD has been reached and the L-bit in the Tx BD is set, the FCS
(32-bit CRC) bytes are appended (if the TC bit is set in the Tx BD), and TENA is negated.
This tells the EEST to generate the illegal Manchester encoding that signifies the end of the
Ethernet frame.
Following the transmission of the CRC, the Ethernet controller writes the frame status bits
into the BD and clears the R-bit. When the end of the current BD has been reached, and the
L-bit is not set (i.e., a frame is comprised of multiple buffers), only the R-bit is cleared.
MC68360 USER’S MANUAL
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