MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 457
MC68EN360CAI25L
Manufacturer Part Number
MC68EN360CAI25L
Description
IC MPU QUICC 25MHZ 240-FQFP
Manufacturer
Freescale Semiconductor
Series
MC68000r
Datasheets
1.MC68EN302AG20BT.pdf
(8 pages)
2.MC68EN360VR25L.pdf
(14 pages)
3.MC68EN360VR25L.pdf
(2 pages)
4.MC68EN360CAI25L.pdf
(962 pages)
Specifications of MC68EN360CAI25L
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Core Size
32 Bit
Cpu Speed
25MHz
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
FQFP
No. Of Pins
240
Supply Voltage Range
4.75V To 5.25V
Rohs Compliant
Yes
Family Name
M68xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
240
Package Type
FQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68EN360CAI25L
Manufacturer:
APLHA
Quantity:
12 000
Company:
Part Number:
MC68EN360CAI25L
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68EN360CAI25L
Manufacturer:
FREESCALE
Quantity:
20 000
- MC68EN302AG20BT PDF datasheet
- MC68EN360VR25L PDF datasheet #2
- MC68EN360VR25L PDF datasheet #3
- MC68EN360CAI25L PDF datasheet #4
- Current page: 457 of 962
- Download datasheet (4Mb)
Reception delays are determined by the CD pin as shown in Figure 7-42. If the CDS bit in
GSMR is zero, then the CD pin is sampled on the rising receive clock edge prior to data
being received. If the CDS bit in GSMR is one, then the CD pin transitions cause data to be
immediately gated into the receiver.
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
NOTE: CTSS = 1 in GSMR. CTSP = 0 or no CTS lost can occur.
(INPUT)
NOTE: CTSS = 0 in GSMR. CTSP = 0 or no CTS lost can occur.
(INPUT)
TCLK
TCLK
CTS
CTS
RTS
RTS
TXD
TXD
while the transmit clock is low.
If the CTSS bit in GSMR is set, all CTS transitions must occur
Figure 7-41. CTS Lost in Synchronous Protocols
Freescale Semiconductor, Inc.
FIRST BIT OF FRAME DATA
For More Information On This Product,
FIRST BIT OF FRAME DATA
CTS SAMPLED LOW HERE
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
CTS SAMPLED HIGH HERE
Serial Communication Controllers (SCCs)
CTS LOST SIGNALED IN FRAME BD
CTS LOST SIGNALED IN FRAME BD
DATA FORCED HIGH
RTS FORCED HIGH
DATA FORCED HIGH
RTS FORCED HIGH
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