MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 945

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

CPU32 1-5, 11
CPU32+ 5-1
CR 7-5
CRC16 7-210
CS 2-10, 6-30, 6-48, 6-67, 6-71
CS0 6-25, 9-5
CSMA/CD 7-235
CSNT40 6-73
CSNTQ 6-73
CSR 7-32
CTS 7-63, 7-101, 7-114, 7-118, 7-120, 7-
Current Instruction Program Counter 5-58
Cycle Length 6-77
D31–D16 2-5
DACK 7-28, 7-33, 7-39
DAPR 7-31
Data Encoding 7-135
Data Length 7-213
Data Movement Instructions 5-19
Data Registers 5-7
Data Strobe 4-4
DBcc instruction 5-3
DEC 7-126
Delayed RTS Mode 7-194
Deriving SWT Timeout 6-36
Deterministic Opcode Tracking 5-59, 5-60,
Development Tools and Support B-1
DFC 4-36
DHR 7-33
Differential Biphase-L 7-118
Differential Manchester 7-118, 7-136
Core 1-5
Instruction Set 5-8
Programming Model 5-6
Registers 5-7
Serial Logic 5-63, 5-65
DFC 5-7
Program Counter 5-7
SFC 5-7
Status Register 5-7
Vector Base Register 5-7
128, 7-129, 7-130, 7-187, 7-190, 7-
192, 7-199, 7-219, 7-223, 7-233, 7-
240, 7-266, 7-358
5-80
D
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68356 USER’S MANUAL
Go to: www.freescale.com
Digital Phase-Locked Loop (DPLL) 7-135
Disable CPU32+ 6-23
Disabling the SCCs 7-139
Disabling the SMCs on the Fly 7-274
DONE 7-28, 7-33, 7-52
Double Bus Fault 4-48, 5-40
Double Bus Fault Monitor 6-4, 6-9
Double Drive RAS Lines 6-63
DPLL 7-117, 7-118
DPLL Error 7-182
DPLL Operation 7-136
DPLL Receive Block Diagram 7-137
DPLL Transmit Block Diagram 7-137
DPRBASE 3-2
DRAM Banks 6-58
DRAM Bus Error 6-63
DRAM Controller
DRAM Controller Overview 6-58
DRAM Counter
DRAM Device 9-9, 9-46
DRAM Normal Access 6-60
DRAM Page Size 6-65
DRAM Port Size 6-65
Address Multiplexing 6-58
Bank Parity 6-62
Bus Error 6-63
Controller Overview 6-58
Devices 9-9, 9-46
Normal Access 6-60
Overview 6-58
Page Size 6-65
Port Size 6-65
SIMM 9-8, 9-45
DRAM-SRAM Performance Summary 6-
External Master Support 6-63
Global Memory Register 6-64
Memory Controller Block Diagram 6-53
Option Register 6-74
Page Mode 6-75
Programming Model 6-64
Refresh 6-64
Refresh Cycle 6-64
Refresh Operation 6-62
Burst Access Support 6-61
Double Drive RAS Lines 6-63
Page Mode Support 6-60
78
Index