MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 234

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

CPU32+
5.7.2.3 MOVE INSTRUCTION. The MOVE instruction table indicates the number of clock
periods needed for the processor to calculate the destination EA and to perform a MOVE or
MOVEA instruction. For entries with CEA or FEA, refer to the appropriate table to calculate
that portion of the instruction time.
Destination EAs are divided by their formats (see CPU32 Reference Manual). The total
number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w)
are included in the total clock cycle number. All timing data assumes two-clock reads and
writes.
When using this table, begin at the top and move downward. Use the first entry that matches
both source and destination addressing modes.
5.7.2.4 SPECIAL-PURPOSE MOVE INSTRUCTION. The special-purpose MOVE instruc-
tion table indicates the number of clock periods needed for the processor to fetch, calculate,
and perform the special-purpose MOVE operation on control registers or a specified EA.
Footnotes indicate when to account for the appropriate EA times. The total number of clock
cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in
the total clock cycle number. All timing data assumes two-clock reads and writes.
5-92
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
X = There is one bus cycle for byte and word operands and two bus cycles for long-word oper-
ands. For long-word bus cycles, add two clocks to the tail and to the number of cycles.
Timing is calculated with the CPU32+ in 16-bit mode.
NOTE: For instructions not explicitly listed, use the MOVE CEA , FEA entry. The source
EA is calculated by the calculate EA table, and the destination EA is calculated by the fetch EA
table, even though the bus cycle is for the source EA.
= An # fetch EA time must be added for this instruction: FEA
Rn, Rn
Rn, (Am)
Rn, (Am)
Rn, (Am)
Rn, CEA
#, CEA
FEA , Rn
FEA , (An)
FEA , (An)
FEA , (An)
CEA , FEA
Instruction
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Head
0
0
0
1
2
1
2
2
2
2
2
Tail
0
0
2
1
2
3
2
2
2
2
2
CEA
OPER
6(0/1/X
2(0/1/0)
2(0/1/0)
4(0/1/X)
5(0/1/X)
5(0/1/X)
6(0/1/X)
6(0/1/X)
6(0/1/X)
Cycles
6(0/1/X
6(0/1/X