MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 188

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
CPU32+
At the present time, T1–T0 = 11 is an undefined condition. It is reserved by Motorola for
future use.
Exception processing for trace starts at the end of normal processing for the traced instruc-
tion and before the start of the next instruction. Exception processing follows the regular
sequence; tracing is disabled so that the trace exception itself is not traced. A vector number
is generated to reference the trace exception vector. The address of the instruction that
caused the trace exception, the trace exception vector offset, the current PC, and a copy of
the SR are saved on the supervisor stack. The saved value of the PC is the address of the
next instruction to be executed.
A trace exception can be viewed as an extension to the function of any instruction. If a trace
exception is generated by an instruction, the execution of that instruction is not complete
until the trace exception processing associated with it is also complete.
If an instruction is aborted by a bus error or address error exception, trace exception pro-
cessing is deferred until the suspended instruction is restarted and completed normally. An
RTE from a bus error or address error will not be traced because of the possibility of con-
tinuing the instruction from the fault.
If an instruction is executed and an interrupt is pending on completion, the trace exception
is processed before the interrupt exception.
If an instruction forces an exception, the forced exception is processed before the trace
exception.
If an instruction is executed and a breakpoint is pending upon completion of the instruction,
the trace exception is processed before the breakpoint.
If an attempt is made to execute an illegal, unimplemented, or privileged instruction while
tracing is enabled, no trace exception will occur because the instruction is not executed. This
is particularly important to an emulation routine that performs an instruction function, adjusts
the stacked PC to beyond the unimplemented instruction, and then returns. The SR on the
stack must be checked to determine if tracing is on before the return is executed. If tracing
is on, trace exception processing must be emulated so that the trace exception handler can
account for the emulated instruction.
Tracing also affects normal operation of the STOP and LPSTOP instructions. If either
instruction begins execution with T1 set, a trace exception will be taken after the instruction
loads the SR. Upon return from the trace handler routine, execution will continue with the
instruction following STOP (LPSTOP), and the processor will not enter the stopped condi-
tion.
5.5.2.11 INTERRUPTS. There are seven levels of interrupt priority and 192 assignable
interrupt vectors within each exception vector table. Careful use of multiple vector tables and
hardware chaining will permit a virtually unlimited number of peripherals to interrupt the pro-
cessor.
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MC68360 USER’S MANUAL
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