MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 623

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

SM—SMC Mode
DM—Diagnostic Mode
TEN—SMC Transmit Enable
REN—SMC Receive Enable
7.11.10.11 SMC TRANSPARENT RECEIVE BUFFER DESCRIPTOR (RX BD). The
reports information about the received data for each buffer using Rx BDs. The CP closes
the current buffer, generates a maskable interrupt, and starts to receive data into the next
buffer after one of the following events:
E—Empty
1. Detecting an overrun error
2. Detecting a full receive buffer
3. Issuing the ENTER HUNT MODE command
OFFSET + 0
OFFSET + 2
OFFSET + 4
OFFSET + 6
NOTE : Entries in boldface must be initialized by the user
00 = GCI or SCIT support
01 = Reserved
10 = UART
11 = Totally transparent operation (must be selected for SMC transparent operation)
00 = Normal operation
01 = Local loopback mode
10 = Echo mode
11 = Reserved
0 = SMC transmitter disabled
1 = SMC transmitter enabled
0 = SMC receiver disabled
1 = SMC receiver enabled
0 = The data buffer associated with this Rx BD has been filled with received data, or
data reception has been aborted due to an error condition. The CPU32+ core is
free to examine or write to any fields of this Rx BD. The CP will not use this BD
again while the E-bit remains zero.
15
E
Once the SMC transmit enable bit is cleared, the bit must not be
reenabled for at least 3 serial clocks.
14
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13
W
Freescale Semiconductor, Inc.
For More Information On This Product,
12
I
11
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MC68360 USER’S MANUAL
Go to: www.freescale.com
10
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NOTES
CM
RX DATA BUFFER POINTER
9
DATA LENGTH
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8
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7
Serial Management Controllers (SMCs)
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6
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5
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4
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3
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2
OV
1
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0
CP