MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 650

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Serial Peripheral Interface (SPI)
The following status bits are written by the SPI after the received data has been placed into
the associated data buffer.
L—Last
OV—Overrun
ME—Multi-Master Error
Data Length
Rx Data Buffer Pointer
7.12.5.5.2 SPI Transmit Buffer Descriptor (Tx BD). Data to be transmitted with the SPI is
presented to the CP by arranging it in buffers referenced by the Tx BD ring. The first word
of the Tx BD contains status and control bits.
The following bits should be prepared by the user before transmission.
7-326
This bit is set by the SPI controller when the buffer is closed due to negation of the SPISEL
pin. This can only occur when the SPI is a slave; otherwise, the ME bit is set.
A receiver overrun occurred during reception. This error can only occur when the SPI is a
slave.
This buffer was closed because the SPISEL pin was asserted when the SPI was operating
as a master. This indicates a synchronization problem between multiple masters on the
SPI bus.
Data length is the number of octets that the CP has written into this BD’s data buffer. It is
written once by the CP as the BD is closed.
The receive buffer pointer, which always points to the first location of the associated data
buffer, must be even. The buffer may reside in either internal or external memory.
OFFSET + 0
OFFSET + 2
OFFSET + 4
OFFSET + 6
0 = This buffer does not contain the last character of the message.
1 = This buffer contains the last character of the message.
15
R
The actual amount of memory allocated for this buffer should be
greater than or equal to the contents of the MRBLR.
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Freescale Semiconductor, Inc.
For More Information On This Product,
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MC68360 USER’S MANUAL
Go to: www.freescale.com
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CM
TX DATA BUFFER POINTER
NOTE
9
DATA LENGTH
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8
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7
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6
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5
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4
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3
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2
UN
1
ME
0