MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 636

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Serial Peripheral Interface (SPI)
CRXB—C/I Channel Buffer Received
MTXB—Monitor Channel Buffer Transmitted
MRXB—Monitor Channel Buffer Received
7.11.14.10 SMC MASK REGISTER (SMCM). The SMCM is an 8-bit, memory-mapped,
read-write register. It has the same bit format as the SMC event register. If a bit in the SMCM
is a one, the corresponding interrupt in the SMC event register will be enabled. If the bit is
zero, the corresponding interrupt in the SMC event register will be masked. The SMCM is
clear upon reset.
7.12 SERIAL PERIPHERAL INTERFACE (SPI)
The SPI allows the QUICC to exchange data between other QUICC chips, the MC68302,
the M68HC11 and M68HC05 microcontroller families, and a number of peripheral devices
such as EEPROMs, real-time clock devices, A/D converters, and ISDN devices.
7.12.1 Overview
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire
interface (receive, transmit, clock, and slave select).
The SPI block consists of transmitter and receiver sections, an independent baud rate gen-
erator, and a control unit. The transmitter and receiver sections use the same clock, which
is derived from the SPI baud rate generator in master mode and generated externally in
slave mode. During an SPI transfer, data is transmitted and received simultaneously. Refer
to Figure 7-80 for the SPI block diagram.
7-312
The C/I receive buffer is full.
The monitor transmit buffer became empty.
The monitor receive buffer is full.
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