ST10F269-T3 STMicroelectronics, ST10F269-T3 Datasheet - Page 108

• Manufacturer Part Number: ST10F269-T3
• Manufacturer: STMicroelectronics

Specifications of ST10F269-T3

• Cpu Family: ST10
• Device Core Size: 16b
• Frequency (max): 32MHz
• Interface Type: ASC/I2C/SSC
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 12KB
• # I/os (max): 111
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: CISC/RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

ST10F269-T3
Figure 55 : Asynchronous Reset Sequence Internal Fetch
Note: 1) RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on
Power-on reset
The asynchronous reset must be used during the power-on of the MCU. Depending on the crystal frequency,
the on-chip oscillator needs about 10ms to 50ms to stabilize. The logic of the MCU does not need a stabilized
clock signal to detect an asynchronous reset, so it is suitable for power-on conditions. To ensure a proper
reset sequence, the RSTIN pin and the RPD pin must be held at low level until the MCU clock signal is
stabilized and the system configuration value on PORT0 is settled.
Hardware reset
The asynchronous reset must be used to recover from catastrophic situations of the application. It may be
triggered by the hardware of the application. Internal hardware logic and application circuitry are
described in Section 18.6 - Reset Circuitry and Figure 58, Figure 59 and Figure 60.
18.1.2 - Synchronous Reset (RSTIN pulse > 1040TCL and RPD pin at high level)
The synchronous reset is a warm reset. It may be generated synchronously to the CPU clock. To be
detected by the reset logic, the RSTIN pulse must be low at least for 4 TCL (2 periods of CPU clock).
Then the I/O pins are set to high impedance and RSTOUT pin is driven low. After the RSTIN level is
detected, a short duration of 12 TCL (6 CPU clocks) maximum elapses, during which pending internal
hold states are cancelled and the current internal access cycle, if any, is completed. External bus cycle is
aborted.
by software. This bit is always cleared on power-on or after any reset sequence.
The internal sequence lasts for 1024 TCL (512 periods of CPU clock). After this duration the pull-down of
RSTIN pin for the bidirectional reset function is released and the RSTIN pin level is sampled. At this step
the sequence lasts 1040 TCL (4 TCL + 12 TCL + 1024 TCL). If the RSTIN pin level is low, the reset
sequence is extended until RSTIN level becomes high. Refer to Figure 56
Note
108/162
The internal pull-down of RSTIN pin is activated if bit BDRSTEN of SYSCON register was previously set
2) 2.1µs typical value.
(f
RPD
CPU Clock
RSTIN
RSTOUT
PORT0
PLL factor
latch command
Internal reset signal
Flash read signal
CPU
If V
is low or when RSTIN pin is internally pulled low, the ST10 reset circuitry disables the bidirectional
reset function and RSTIN pin is no more pulled low. The reset is processed as an asynchronous
reset.
= f
RPD
XTAL
/ 2), else it is 4 CPU clock cycles (8 TCL).
voltage drops below the RPD pin threshold (typically 2.5V for V
Reset Condition
Asynchronous
INTERNAL FETCH
Reset Configuration
6 or 8 TCL
1
Flash under reset for internal charge pump ramping up
2
3
1)
Latching point of PORT0
for PLL configuration
2.5µs max.
2)
DD
Latching point of PORT0
for remaining bits
= 5V) when RSTIN pin
from Flash
1st fetch