ST10F269-T3 STMicroelectronics, ST10F269-T3 Datasheet - Page 34

• Manufacturer Part Number: ST10F269-T3
• Manufacturer: STMicroelectronics

Specifications of ST10F269-T3

• Cpu Family: ST10
• Device Core Size: 16b
• Frequency (max): 32MHz
• Interface Type: ASC/I2C/SSC
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 12KB
• # I/os (max): 111
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: CISC/RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

ST10F269-T3
6 - CENTRAL PROCESSING UNIT (CPU)
The CPU includes a 4-stage instruction pipeline, a
16-bit arithmetic and logic unit (ALU) and dedi-
cated SFRs. Additional hardware has been added
for a separate multiply and divide unit, a bit-mask
generator and a barrel shifter.
Most of the ST10F269-T3’s instructions can be
executed in one instruction cycle which requires
62.5ns at 32MHz CPU clock. For example, shift
and rotate instructions are processed in one
instruction cycle independent of the number of
bits to be shifted.
Multiple-cycle instructions have been optimized:
branches are carried out in 2 cycles, 16 x 16-bit
multiplication in 5 cycles and a 32/16-bit division
in 10 cycles.
The jump cache reduces the execution time of
repeatedly performed jumps in a loop, from
2 cycles to 1 cycle.
Figure 9 : CPU Block Diagram (MAC Unit not included)
34/162
256K Byte
memory
Flash
32
Exec. Unit
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
Data Pg. Ptrs
Instr. Ptr
STKOV
STKUN
SYSCON
Pipeline
PSW
4-Stage
SP
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
ADDRSEL 4
Code Seg. Ptr.
Bit-Mask Gen.
Mul./Div.-HW
Barrel-Shift
CPU
16-Bit
MDH
MDL
ALU
CP
The CPU uses a bank of 16 word registers to run
the current context. This bank of General Purpose
Registers (GPR) is physically stored within the
on-chip Internal RAM (IRAM) area. A Context
Pointer (CP) register determines the base
address of the active register bank to be accessed
by the CPU.
The number of register banks is only restricted by
the available Internal RAM space. For easy
parameter passing, a register bank may overlap
others.
A system stack of up to 1024 bytes is provided as
a storage for temporary data. The system stack is
allocated in the on-chip RAM area, and it is
accessed by the CPU via the stack pointer (SP)
register.
Two separate SFRs, STKOV and STKUN, are
implicitly compared against the stack pointer
value upon each stack access for the detection of
a stack overflow or underflow.
Registers
General
Purpose
R15
R0
16
16
2K Byte
Internal
Bank
Bank
Bank
RAM
n
0
i