ST10F269-T3 STMicroelectronics, ST10F269-T3 Datasheet - Page 61

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ST10F269-T3

Manufacturer Part Number
ST10F269-T3
Description
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST10F269-T3

Cpu Family
ST10
Device Core Size
16b
Frequency (max)
32MHz
Interface Type
ASC/I2C/SSC
Program Memory Type
Flash
Program Memory Size
256KB
Total Internal Ram Size
12KB
# I/os (max)
111
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
On-chip Adc
16-chx10-bit
Instruction Set Architecture
CISC/RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / Rohs Status
Supplier Unconfirmed

Available stocks

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Part Number:
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Quantity:
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0
12.3 - PORT0
The two 8-bit ports P0H and P0L represent the
higher and lower part of PORT0, respectively.
Both halves of PORT0 can be written (via a PEC
transfer) without effecting the other half.
P0L (FF00h / 80h)
P0H (FF02h / 81h)
DP0L (F100h / 80h)
DP0H (F102h / 81h)
P0X.y
DP0X.y
15
15
-
-
15
15
-
-
14
14
-
-
14
14
-
-
13
13
-
-
12
12
13
13
-
-
-
-
Port Data Register P0H or P0L Bit y
Port Direction Register DP0H or DP0L Bit y
DP0X.y = 0: Port line P0X.y is an input (high-impedance)
DP0X.y = 1: Port line P0X.y is an output
11
11
-
-
12
12
-
-
10
10
-
-
11
11
9
9
-
-
-
-
8
8
-
-
10
10
-
-
DP0H.7 DP0H.6 DP0H.5 DP0H.4 DP0H.3 DP0H.2 DP0H.1 DP0H.0
DP0L.7 DP0L.6 DP0L.5 DP0L.4 DP0L.3 DP0L.2 DP0L.1 DP0L.0
RW
RW
7
7
9
9
-
-
RW
RW
6
6
8
8
-
-
ESFR
ESFR
SFR
SFR
P0H.7 P0H.6 P0H.5 P0H.4 P0H.3 P0H.2 P0H.1 P0H.0
P0L.7 P0L.6 P0L.5 P0L.4 P0L.3 P0L.2 P0L.1 P0L.0
RW
RW
If this port is used for general purpose I/O, the
direction of each line can be configured via the
corresponding direction registers DP0H and
DP0L.
7
7
RW
RW
5
5
RW
RW
6
6
RW
RW
4
4
RW
RW
5
5
RW
RW
RW
RW
3
3
4
4
RW
RW
3
3
RW
RW
2
2
Reset Value: --00h
Reset Value: --00h
Reset Value: --00h
Reset Value: --00h
RW
RW
2
2
ST10F269-T3
RW
RW
1
1
RW
RW
1
1
61/162
RW
RW
RW
RW
0
0
0
0

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