ST10F269-T3 STMicroelectronics, ST10F269-T3 Datasheet - Page 65

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ST10F269-T3

Manufacturer Part Number
ST10F269-T3
Description
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST10F269-T3

Cpu Family
ST10
Device Core Size
16b
Frequency (max)
32MHz
Interface Type
ASC/I2C/SSC
Program Memory Type
Flash
Program Memory Size
256KB
Total Internal Ram Size
12KB
# I/os (max)
111
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
On-chip Adc
16-chx10-bit
Instruction Set Architecture
CISC/RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / Rohs Status
Supplier Unconfirmed

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
ST10F269-T3
Quantity:
6 262
Part Number:
ST10F269-T3
Manufacturer:
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0
Figure 23 : PORT1 I/O and Alternate Functions
When an external bus mode is enabled, the
direction of the port pin and the loading of data
into the port output latch are controlled by the bus
controller hardware.
The input of the port Buffer latch is disconnected
from the internal bus and is switched to the line
labeled “Alternate Data Output” via a multiplexer.
The alternate data is the 16-bit intra-segment
Figure 24 : Block Diagram of a PORT1 Pin
PORT1
General Purpose Input/Output
Alternate Function
P1H
P1L
Write P1H.y / P1L.y
Write DP1H.y / DP1L.y
Read DP1H.y / DP1L.y
Read P1H.y / P1L.y
Port Output
P1H.7
P1H.6
P1H.5
P1H.4
P1H.3
P1H.2
P1H.1
P1H.0
P1L.7
P1L.6
P1L.5
P1L.4
P1L.3
P1L.2
P1L.1
P1L.0
Direction
Latch
Latch
MUX
8/16-bit Demultiplexed Bus
Port Data
Output
1
0
Alternate
Function
Enable
Alternate
Data
Output
“1”
a)
address. While an external bus mode is enabled,
the user software should not write to the port
output latch, otherwise unpredictable results may
occur. When the external bus modes are disabled,
the contents of the direction register last written by
the user becomes active.
The Figure 24 shows the structure of a PORT1
pin.
1
0
1
0
MUX
MUX
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Clock
Latch
Input
CAPCOM2 Capture Inputs only
Output
Buffer
b)
CC27IO
CC26IO
CC25IO
CC24IO
ST10F269-T3
y = 7...0
P1H.y
P1L.y
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