ST10F269-T3 STMicroelectronics, ST10F269-T3 Datasheet - Page 44

• Manufacturer Part Number: ST10F269-T3
• Manufacturer: STMicroelectronics

Specifications of ST10F269-T3

• Cpu Family: ST10
• Device Core Size: 16b
• Frequency (max): 32MHz
• Interface Type: ASC/I2C/SSC
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 12KB
• # I/os (max): 111
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: CISC/RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

ST10F269-T3
8 - INTERRUPT SYSTEM
The interrupt response time for internal program
execution is from 156.25ns to 375ns at 32MHz
CPU clock.
The ST10F269-T6 architecture supports several
mechanisms for fast and flexible response to
service requests that can be generated from
various sources (internal or external) to the
microcontroller. Any of these interrupt requests
can be serviced by the Interrupt Controller or by
the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where
the current program execution is suspended and a
branch to the interrupt vector table is performed,
just one cycle is ‘stolen’ from the current CPU
activity to perform a PEC service. A PEC service
implies a single Byte or Word data transfer
between any two memory locations with an
additional increment of either the PEC source or
destination pointer. An individual PEC transfer
counter is implicitly decremented for each PEC
service except when performing in the continuous
transfer mode. When this counter reaches zero, a
standard
corresponding source related vector location.
PEC services are very well suited to perform the
transmission or the reception of blocks of data.
The ST10F269-T3 has 8 PEC channels, each of
them offers such fast interrupt-driven data transfer
capabilities.
EXISEL (F1DAh / EDh)
44/162
EXIxSS
15
EXI7SS
RW
14
EXIxSS
4...7
interrupt
0
1
2
3
13
EXI6SS
External Interrupt x Source Selection (x=7...0)
‘00’: Input from associated Port 2 pin.
‘01’: Input from “alternate source”.
‘10’: Input from Port 2 pin ORed with “alternate source”.
‘11’: Input from Port 2 pin ANDed with “alternate source”.
RW
12
is
performed
11
EXI5SS
RW
10
to
9
EXI4SS
Port 2 pin
P2.12...15
RW
P2.10
P2.11
P2.8
P2.9
the
8
ESFR
An interrupt control register which contains an
interrupt request flag, an interrupt enable flag and
an interrupt priority bit-field is dedicated to each
existing interrupt source. Thanks to its related
register, each source can be programmed to one
of sixteen interrupt priority levels. Once starting to
be processed by the CPU, an interrupt service
can only be interrupted by a higher prioritized
service request. For the standard interrupt
processing, each of the possible interrupt sources
has a dedicated vector location.
Software interrupts are supported by means of the
‘TRAP’
individual trap (interrupt) number.
8.1 - External Interrupts
Fast external interrupt inputs are provided to
service external interrupts with high precision
requirements. These fast interrupt inputs feature
programmable edge detection (rising edge, falling
edge or both edges).
Fast external interrupts may also have interrupt
sources selected from other peripherals; for
example the CANx controller receive signal
(CANx_RxD) can be used to interrupt the system.
This new function is controlled using the ‘External
Interrupt Source Selection’ register EXISEL.
7
EXI3SS
RW
6
instruction
5
EXI2SS
RW
4
in
Alternate Source
Not used (zero)
RTCSI (Timed)
RTCAI (Alarm)
CAN1_RxD
CAN2_RxD
combination
3
EXI1SS
RW
Reset Value: 0000h
2
1
EXI0SS
with
RW
0
an