ST10F269-T3 STMicroelectronics, ST10F269-T3 Datasheet - Page 97

• Manufacturer Part Number: ST10F269-T3
• Manufacturer: STMicroelectronics

Specifications of ST10F269-T3

• Cpu Family: ST10
• Device Core Size: 16b
• Frequency (max): 32MHz
• Interface Type: ASC/I2C/SSC
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 12KB
• # I/os (max): 111
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: CISC/RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

15 - CAN MODULES
The two integrated CAN modules (CAN1 and
CAN2) are identical and handle the completely
autonomous transmission and reception of CAN
frames according to the CAN specification V2.0
part B (active).
Each on-chip CAN module can receive and
transmit standard frames with 11-bit identifiers as
well as extended frames with 29-bit identifiers.
These two CAN modules are both identical to the
CAN module of the ST10F167.
Because of duplication of the CAN controllers, the
following adjustments are to be considered:
– Same internal register addresses of both CAN
– The CAN1 transmit line (CAN1_TxD) is the
– The CAN2 transmit line (CAN2_TxD) is the
– Interrupt request line of the CAN1 module is
– The CAN modules must be selected with
– The reset default configuration is: CAN1 is
15.1 - CAN Modules Memory Mapping
15.1.1 - CAN1
Address range 00’EF00h - 00’EFFFh is reserved
for the CAN1 Module access. CAN1 is enabled by
setting XPEN bit 2 of the SYSCON register and by
setting bit 0 of the XPERCON register. Accesses
to the CAN Module use demultiplexed addresses
and a 16-bit data bus (Byte accesses are
possible). Two wait states give an access time of
125ns at 32MHz CPU clock. No tri-state wait
states are used.
controllers, but with base addresses differing in
address bit A8; separate chip select for each
CAN module. Refer to Chapter 4 - Memory Or-
ganization.
alternate function of the Port P4.6 pin and the
receive line (CAN1_RxD) is the alternate
function of the Port P4.5 pin.
alternate function of the Port P4.7 pin and the
receive line (CAN2_RxD) is the alternate
function of the Port P4.4 pin.
connected to the XBUS interrupt line XP0,
interrupt of the CAN2 module is connected to
the line XP1.
corresponding CANxEN bit of XPERCON register
before the bit XPEN of SYSCON register is set.
enabled, CAN2 is disabled.
15.1.2 - CAN2
Address range 00’EE00h - 00’EEFFh is reserved
for the CAN2 Module access. CAN2 is enabled by
setting XPEN bit 2 of the SYSCON register and by
setting bit 1 of the XPERCON register. Accesses
to the CAN Module use demultiplexed addresses
and a 16-bit data bus (Byte accesses are
possible). Two wait states give an access time of
125ns at 32MHz CPU clock. No tri-state wait
states are used.
Note: If one or both CAN modules is used,
15.2 - CAN Bus Configurations
Depending on application, CAN bus configuration
may be one single bus with a single or multiple
interfaces or a multiple bus with a single or
multiple interfaces. The ST10F269-T3 is able to
support these 2 cases.
Single CAN Bus
The
configuration may be implemented using 2 CAN
transceivers as shown in Figure 47.
Figure 47 : Single CAN Bus Multiple Interfaces,
Multiple Transceivers
single
Port 4 cannot be programmed to output all
8 segment address lines. Thus, only
4 segment address lines can be used,
reducing the external memory space to
5M Bytes (1M Byte per CS line).
CAN_H
CAN_H
Transceiver
RxD TxD
CAN
CAN1
CAN
Bus
CAN bus
Transceiver
RxD TxD
CAN2
multiple
CAN
ST10F269-T3
interfaces
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