ST10F269-T3 STMicroelectronics, ST10F269-T3 Datasheet - Page 38

• Manufacturer Part Number: ST10F269-T3
• Manufacturer: STMicroelectronics

Specifications of ST10F269-T3

• Cpu Family: ST10
• Device Core Size: 16b
• Frequency (max): 32MHz
• Interface Type: ASC/I2C/SSC
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 12KB
• # I/os (max): 111
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: CISC/RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

ST10F269-T3
Table 4 : Instruction Set Summary
6.3 - MAC Coprocessor Specific Instructions
The following table gives an overview of the MAC
instruction set. All the mnemonics are listed with
the addressing modes that can be used with each
instruction.
For each combination of mnemonic and address-
ing mode this table indicates if it is repeatable or
not.
New addressing capabilities enable the CPU to
supply the MAC with up to 2 operands per instruc-
tion cycle. MAC instructions: multiply, multi-
ply-accumulate, 32-bit signed arithmetic operations
and the CoMOV transfer instruction have been
38/162
JNBS
CALLA, CALLI, CALLR
CALLS
PCALL
TRAP
PUSH, POP
SCXT
RET
RETS
RETP
RETI
SRST
IDLE
PWRDN
SRVWDT
DISWDT
EINIT
ATOMIC
EXTR
EXTP(R)
EXTS(R)
NOP
Mnemonic
Jump relative and set bit if direct bit is not set
Call absolute/indirect/relative subroutine if condition is met
Call absolute subroutine in any code segment
operand
Return from inter-segment subroutine
Return from intra-segment subroutine and pop direct
word register from system stack
Return from interrupt service subroutine
Enter Power Down Mode (supposes NMI-pin being low)
Service Watchdog Timer
Disable Watchdog Timer
Signify End-of-Initialization on RSTOUT-pin
Begin ATOMIC sequence
Begin EXTended Register sequence
Begin EXTended Page (and Register) sequence
Begin EXTended Segment (and Register) sequence
Push direct word register onto system stack and call absolute subroutine
Call interrupt service routine via immediate trap number
Push/pop direct word register onto/from system stack
Push direct word register onto system stack and update register with word
Return from intra-segment subroutine
Software Reset
Enter Idle Mode
Null operation
Description
added to the standard instruction set. Full details
are provided in the ‘ST10 Family Programming
Manual’. Double indirect addressing requires two
pointers. Any GPR can be used for one pointer, the
other pointer is provided by one of two specific
SFRs IDX0 and IDX1. Two pairs of offset registers
QR0/QR1 and QX0/QX1 are associated with each
pointer (GPR or IDX
The GPR pointer allows access to the entire
memory space, but IDX
Dual-Port RAM, except for the CoMOV instruction.
i
).
i
are limited to the internal
Bytes
2 / 4
2 / 4
4
2
4
4
4
4
2
2
4
2
2
2
4
4
4
4
4
2
2
2