ST10F269-T3 STMicroelectronics, ST10F269-T3 Datasheet - Page 46

• Manufacturer Part Number: ST10F269-T3
• Manufacturer: STMicroelectronics

Specifications of ST10F269-T3

• Cpu Family: ST10
• Device Core Size: 16b
• Frequency (max): 32MHz
• Interface Type: ASC/I2C/SSC
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 12KB
• # I/os (max): 111
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: CISC/RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

ST10F269-T3
Table 7 : Interrupt Sources (continued)
Hardware traps are exceptions or error conditions
that arise during run-time. They cause immediate
non-maskable system reaction similar to a
standard interrupt service (branching to a
dedicated vector table location).
The occurrence of a hardware trap is additionally
signified by an individual bit in the trap flag
register (TFR). Except when another higher
prioritized trap service is in progress, a hardware
trap will interrupt any other program execution.
Hardware trap services cannot not be interrupted
by standard interrupt or by PEC interrupts.
8.3 - Interrupt Control Registers
All interrupt control registers are identically
organized. The lower 8 bits of an interrupt control
register contain the complete interrupt status
information of the associated source, which is
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CAPCOM Timer 1
CAPCOM Timer 7
CAPCOM Timer 8
GPT1 Timer 2
GPT1 Timer 3
GPT1 Timer 4
GPT2 Timer 5
GPT2 Timer 6
GPT2 CAPREL Register
A/D Conversion Complete
A/D Overrun Error
ASC0 Transmit
ASC0 Transmit Buffer
ASC0 Receive
ASC0 Error
SSC Transmit
SSC Receive
SSC Error
PWM Channel 0...3
CAN1 Interface
CAN2 Interface
FLASH Ready / Busy
PLL Unlock/OWD
Source of Interrupt or PEC
Service Request
Request
S0TBIR
PWMIR
ADCIR
ADEIR
SCTIR
SCRIR
SCEIR
S0RIR
S0EIR
XP0IR
XP1IR
XP2IR
S0TIR
XP3IR
CRIR
T1IR
T7IR
T8IR
T2IR
T3IR
T4IR
T5IR
T6IR
Flag
S0TBIE
PWMIE
Enable
ADCIE
ADEIE
SCRIE
SCEIE
S0RIE
SCTIE
S0TIE
S0EIE
XP0IE
XP1IE
XP2IE
XP3IE
CRIE
Flag
T1IE
T7IE
T8IE
T2IE
T3IE
T4IE
T5IE
T6IE
required during one round of prioritization, the
upper 8 bits of the respective register are
reserved. All interrupt control registers are bit
addressable and all bits can be read or written via
software.
This
programmed or modified with just one instruction.
When
through instructions which operate on Word data
types, their upper 8 bits (15...8) will return zeros,
when read, and will discard written data.
The layout of the Interrupt Control registers shown
below applies to each xxIC register, where xx
stands for the mnemonic for the respective
source.
allows
Interrupt
S0TBINT
PWMINT
ADCINT
ADEINT
SCRINT
SCEINT
S0RINT
SCTINT
S0TINT
S0EINT
XP0INT
XP1INT
XP2INT
XP3INT
accessing
Vector
CRINT
T1INT
T7INT
T8INT
T2INT
T3INT
T4INT
T5INT
T6INT
each
interrupt
00’00ACh
00’00BCh
00’00FCh
00’008Ch
00’009Ch
00’00A0h
00’00A4h
00’00A8h
00’011Ch
00’00B0h
00’00B4h
00’00B8h
00’010Ch
Location
00’0084h
00’00F4h
00’00F8h
00’0088h
00’0090h
00’0094h
00’0098h
00’0100h
00’0104h
00’0108h
interrupt
Vector
control
source
Number
Trap
3Dh
3Eh
2Ah
2Bh
2Ch
2Dh
2Eh
21h
22h
23h
24h
25h
26h
27h
28h
29h
47h
2Fh
3Fh
40h
41h
42h
43h
registers
to
be