ST10F269-T3 STMicroelectronics, ST10F269-T3 Datasheet - Page 157

• Manufacturer Part Number: ST10F269-T3
• Manufacturer: STMicroelectronics

Specifications of ST10F269-T3

• Cpu Family: ST10
• Device Core Size: 16b
• Frequency (max): 32MHz
• Interface Type: ASC/I2C/SSC
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 12KB
• # I/os (max): 111
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: CISC/RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

21.4.14 - High-Speed Synchronous Serial Interface (SSC) Timing
21.4.14.1 Master Mode
V
Note: 1. Timing guaranteed by design.
The formula for SSC Clock Cycle time is: t
Where <SSCBR> represents the content of the SSC Baud rate register, taken as unsigned 16-bit integer.
Figure 81 : SSC Master Timing
Notes: 1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge (drawn
t
t
CC
t
t
t
t
t
t
t
t
t
307p
308p
300
301
302
303
304
305
306
307
308
Symbol
= 5V ±10%, V
in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transition (SSCPO = 0b).
2. The bit timing is repeated for all bits to be transmitted or received.
SCLK
MTSR
MRST
CC SSC clock cycle time
CC SSC clock high time
CC SSC clock low time
CC SSC clock rise time
CC SSC clock fall time
CC Write data valid after shift edge
CC Write data hold after shift edge
SR Read data setup time before
SR Read data hold time after latch
SR Read data setup time before
SR Read data hold time after latch
latch edge, phase error
detection on (SSCPEN = 1)
edge, phase error detection on
(SSCPEN = 1)
latch edge, phase error
detection off (SSCPEN = 0)
edge, phase error detection off
(SSCPEN = 0)
1)
SS
= 0V, CPU clock = 32MHz, T
Parameter
t
305
1st.In Bit
t
307
t
300
1st Out Bit
t
308
t
t
301
305
t
304
1
300
Maximum Baud rate = 8M Baud
2nd Out Bit
Minimum
t
2nd.In Bit
= 4 TCL * (<SSCBR> + 1)
302
46.875
31.25
52.5
52.5
62.5
125
(<SSCBR> = 0001h)
-2
–
–
–
0
A
= -40 to +125°C, C
t
303
t
306
Maximum
2)
10
10
15
–
–
–
–
–
–
–
–
t
L
305
= 50pF
Last.In Bit
t
307
2TCL+15.625
(<SSCBR>=0001h-FFFFh) Unit
t
t
Minimum
Last Out Bit
300
300
8 TCL
4TCL
2TCL
Variable Baud rate
t
308
/2 - 10
/2 - 10
-2
–
–
–
0
262144 TCL
Maximum
ST10F269-T3
10
10
15
–
–
–
–
–
–
–
157/162
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns