ST10F269-T3 STMicroelectronics, ST10F269-T3 Datasheet - Page 115

• Manufacturer Part Number: ST10F269-T3
• Manufacturer: STMicroelectronics

Specifications of ST10F269-T3

• Cpu Family: ST10
• Device Core Size: 16b
• Frequency (max): 32MHz
• Interface Type: ASC/I2C/SSC
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 12KB
• # I/os (max): 111
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: CISC/RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

EXICON (F1C0h / E0h
EXxIN inputs are normally sampled interrupt
inputs. However, the Power Down mode circuitry
uses them as level-sensitive inputs.
An EXxIN (x = 3...0) Interrupt Enable bit (bit
CCxIE in respective CCxIC register) need not be
set to bring the device out of Power Down mode.
An external RC circuit must be connected to RPD
pin, as shown in the Figure 61.
Figure 61 : External R0C0 Circuit on RPD Pin For
Exiting Powerdown Mode with External Interrupt
To exit Power Down mode with an external
interrupt, an EXxIN (x = 7...0) pin has to be
asserted for at least 40ns.
EXIxES(x=7...0)
15
EXI7ES
RW
ST10F269-Q3
14
RPD
13
EXI6ES
RW
12
External Interrupt x Edge Selection Field (x=7...0)
0 0:
0 1:
1 0:
1 1:
+
V
DD
Fast external interrupts disabled: standard mode
EXxIN pin not taken in account for entering/exiting Power Down mode.
Interrupt on positive edge (rising)
Enter Power Down mode if EXiIN = ‘0’, exit if EXxIN = ‘1’ (referred as ‘high’ active level)
Interrupt on negative edge (falling)
Enter Power Down mode if EXiIN = ‘1’, exit if EXxIN = ‘0’ (referred as ‘low’ active level)
Interrupt on any edge (rising or falling)
Always enter Power Down mode, exit if EXxIN level changed.
11
EXI5ES
R0
C0
RW
220kΩ minimum
1µF Typical
10
9
EXI4ES
RW
8
ESFR
This signal enables the internal oscillator and PLL
circuitry, and also turns on the weak pull-down
(see Figure 62).
The discharge of the external capacitor provides a
delay that allows the oscillator and PLL circuits to
stabilize before the internal CPU and Peripheral
clocks are enabled. When the RPD voltage drops
below the threshold voltage (about 2.5V), the
Schmitt trigger clears Q2 flip-flop, thus enabling
the CPU and Peripheral clocks, and the device
resumes code execution.
If the Interrupt was enabled (bit CCxIE=’1’ in the
respective CCxIC register) before entering Power
Down mode, the device executes the interrupt
service routine, and then resumes execution after
the PWRDN instruction (see note below).
If the interrupt was disabled, the device executes
the instruction following PWRDN instruction, and
the Interrupt Request Flag (bit CCxIR in the
respective CCxIC register) remains set until it is
cleared by software.
Note:
7
EXI3ES
RW
6
Due
instruction that follows the PWRDN
instruction is executed before the CPU
performs a call of the interrupt service
routine when exiting power-down mode
5
EXI2ES
to
RW
the
4
internal
3
EXI1ES
RW
Reset Value: 0000h
2
ST10F269-T3
pipeline,
1
EXI0ES
RW
115/162
0
the