ST10F269-T3 STMicroelectronics, ST10F269-T3 Datasheet - Page 158
ST10F269-T3
Manufacturer Part Number
ST10F269-T3
Description
Manufacturer
STMicroelectronics
Datasheet
1.ST10F269-T3.pdf
(162 pages)
Specifications of ST10F269-T3
Cpu Family
ST10
Device Core Size
16b
Frequency (max)
32MHz
Interface Type
ASC/I2C/SSC
Program Memory Type
Flash
Program Memory Size
256KB
Total Internal Ram Size
12KB
# I/os (max)
111
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
On-chip Adc
16-chx10-bit
Instruction Set Architecture
CISC/RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / Rohs Status
Supplier Unconfirmed
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ST10F269-T3
21.4.14.2 Slave mode
V
The formula for SSC Clock Cycle time is: t
Where <SSCBR> represents the content of the SSC Baud rate register, taken as unsigned 16-bit integer.
Figure 82 : SSC Slave Timing
Notes: 1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge (drawn
158/162
t
t
318p
t
t
t
t
t
t
t
t
t
CC
317p
Symbol
310
311
312
313
314
315
316
317
318
= 5V ±10%, V
1
in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transition (SSCPO = 0b).
2. The bit timing is repeated for all bits to be transmitted or received.
SCLK
MRST
MTSR
CC Write data valid after shift edge
CC Write data hold after shift edge
SR SSC clock cycle time
SR SSC clock high time
SR SSC clock low time
SR SSC clock rise time
SR SSC clock fall time
SR Read data setup time before latch edge,
SR Read data hold time after latch edge,
SR Read data setup time before latch edge,
SR Read data hold time after latch edge,
phase error detection on (SSCPEN = 1)
phase error detection on (SSCPEN = 1)
phase error detection off (SSCPEN = 0)
phase error detection off (SSCPEN = 0)
1)
SS
= 0V, CPU clock = 32MHz, T
Parameter
t
315
t
1st.In Bit
317
t
310
1st Out Bit
t
318
t
t
315
311
t
314
310
2nd Out Bit
t
= 4 TCL * (<SSCBR> + 1)
2nd.In Bit
Maximum Baud rate=6.25MBd
312
Minimum
109.375
78.125
A
41.25
(<SSCBR> = 0001h)
52.5
52.5
125
= -40 to +125°C, C
6
t
–
–
–
0
313
t
316
2)
Maximum
45.25
10
10
–
–
–
–
–
–
–
–
t
L
315
= 50pF
t
Last.In Bit
317
Last Out Bit
(<SSCBR>=0001h-FFFFh)
t
t
2TCL + 10
Minimum
310
310
4TCL +
6TCL +
t
15.625
15.625
8 TCL
318
Variable Baud rate
/2 - 10
/2 - 10
6
–
–
–
0
262144 TCL
2 TCL + 14
Maximum
10
10
–
–
–
–
–
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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