ST10F269-T3 STMicroelectronics, ST10F269-T3 Datasheet - Page 52

• Manufacturer Part Number: ST10F269-T3
• Manufacturer: STMicroelectronics

Specifications of ST10F269-T3

• Cpu Family: ST10
• Device Core Size: 16b
• Frequency (max): 32MHz
• Interface Type: ASC/I2C/SSC
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 12KB
• # I/os (max): 111
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: CISC/RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

ST10F269-T3
Figure 15 : Block Diagram of GPT1
10.2 - GPT2
The GPT2 module provides precise event control
and time measurement. It includes two timers (T5,
T6) and a capture/reload register (CAPREL). Both
timers can be clocked with an input clock which is
derived from the CPU clock via a programmable
prescaler or with external signals. The count
direction
programmable by software or may additionally be
altered dynamically by an external signal on a port
pin (TxEUD). Concatenation of the timers is
supported via the output toggle latch (T6OTL) of
timer T6 which changes its state on each timer
overflow/underflow.
The state of this latch may be used to clock timer
T5, or it may be output on a port pin (T6OUT). The
overflow / underflow of timer T6 can additionally
be used to clock the CAPCOM timers T0 or T1,
Table 12 : GPT2 Timer Input Frequencies, Resolution and Period
52/162
Pre-scaler factor
Input Freq
Resolution
Period maximum
f
CPU
= 32MHz
CPU Clock
CPU Clock
CPU Clock
T3EUD
T2EUD
T4EUD
T2IN
T3IN
(up/down)
T4IN
2
2
2
n
n
n
8.19ms
125ns
n=3...10
n=3...10
8MHz
n=3...10
000b
4
for
16.4ms
250ns
4MHz
001b
each
8
T2
Mode
Control
T3
Mode
Control
T4
Mode
Control
timer
32.8ms
500ns
2MHz
010b
16
Timer Input Selection T5I / T6I
is
Reload
Reload
Capture
Capture
65.5ms
1MHz
011b
1µs
32
and to cause a reload from the CAPREL register.
The CAPREL register may capture the contents of
timer T5 based on an external signal transition on
the corresponding port pin (CAPIN), and timer T5
may optionally be cleared after the capture
procedure. This allows absolute time differences
to be measured or pulse multiplication to be
performed without software overhead.
The capture trigger (timer T5 to CAPREL) may
also be generated upon transitions of GPT1 timer
T3
advantageous when T3 operates in Incremental
Interface Mode.
Table 12 lists the timer input frequencies,
resolution and periods for each pre-scaler option
at 32MHz CPU clock. This also applies to the
Gated Timer Mode of T6 and to the auxiliary timer
T5 in Timer and Gated Timer Mode.
U/D
GPT1 Timer T3
GPT1 Timer T4
GPT1 Timer T2
inputs
500KHz
131ms
100b
2µs
64
U/D
U/D
T3IN
262.1ms
250KHz
101b
128
4µs
and/or
T3OTL
524.3ms
125KHz
T3EUD.
110b
256
8µs
Request
Interrupt
Request
Interrupt
Request
Interrupt
T3OUT
62.5KHz
This
1.05s
111b
16µs
512
is